公开(公告)号：US10256097B2

公开(公告)日：2019-04-09

申请号：US15846591

申请日：2017-12-19

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Roland Rupp ,  Francisco Javier Santos Rodriguez ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/808 ,  H01L29/861 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/16 ,  H01L29/739

Abstract: A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body.

公开(公告)号：US20180350968A1

公开(公告)日：2018-12-06

申请号：US16054419

申请日：2018-08-03

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Romain Esteve ,  Dethard Peters ,  Roland Rupp ,  Ralf Siemieniec

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L27/06 ,  H01L29/04 ,  H01L29/36 ,  H01L29/872 ,  H01L29/861

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

公开(公告)号：US20180331204A1

公开(公告)日：2018-11-15

申请号：US15979050

申请日：2018-05-14

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/66 ,  G06F17/50 ,  H01L27/02

Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.

公开(公告)号：US10120287B2

公开(公告)日：2018-11-06

申请号：US15249758

申请日：2016-08-29

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Rudolf Elpelt ,  Romain Esteve

IPC: G03F7/20 ,  H01L21/027 ,  H01L23/544 ,  H01L29/06 ,  H01L29/16 ,  H01L29/36 ,  H01L21/04 ,  H01L29/66

Abstract: A beam modifier device is provided that includes scattering portions in which particles vertically impinging on an exposure surface of the beam modifier device are deflected from a vertical direction. A total permeability for the particles changes along a lateral direction parallel to the exposure surface.

公开(公告)号：US20180315845A1

公开(公告)日：2018-11-01

申请号：US16024589

申请日：2018-06-29

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/423 ,  H01L29/167 ,  H01L29/16 ,  H01L29/10 ,  H01L29/861

CPC classification number: H01L29/7805 ,  H01L21/046 ,  H01L29/045 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861

Abstract: A semiconductor device includes a gate trench formed in a semiconductor body and having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, a source region and a drift region of a first conductivity type formed in the semiconductor body, a body region of a second conductivity type arranged between the source region and the drift region and adjoining the first sidewall of the gate trench, and a diode region of the second conductivity type adjoining the second sidewall of the gate trench. A pn junction is formed between the diode region and the drift region and adjoins the bottom of the gate trench. The drift region has a locally increased doping concentration in a region between a pn junction at the border between the body region and the drift region and a lower end of the diode region.

公开(公告)号：US20180308938A1

公开(公告)日：2018-10-25

申请号：US15959661

申请日：2018-04-23

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Daniel Kueck

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.

公开(公告)号：US10074741B2

公开(公告)日：2018-09-11

申请号：US15057704

申请日：2016-03-01

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Romain Esteve ,  Dethard Peters ,  Roland Rupp ,  Ralf Siemieniec

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L27/06 ,  H01L29/872 ,  H01L29/36 ,  H01L29/861 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/7804 ,  H01L27/0629 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/401 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

公开(公告)号：US20180248000A1

公开(公告)日：2018-08-30

申请号：US15957765

申请日：2018-04-19

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A vertical transistor device includes a silicon-carbide substrate, a gate trench formed in the silicon-carbide substrate, a body region adjacent the gate trench, a source region adjacent the gate trench and above the body region, and a dielectric material covering a bottom and a sidewall of the gate trench. A thickness of the dielectric material is greater at the bottom of the gate trench than along the sidewall of the gate trench. Further vertical transistor device embodiments and corresponding methods of manufacture are also described.

公开(公告)号：US20180122931A1

公开(公告)日：2018-05-03

申请号：US15858730

申请日：2017-12-29

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/04 ,  H01L29/66 ,  H01L21/04 ,  H01L29/167 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L29/7805 ,  H01L21/046 ,  H01L29/045 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861

Abstract: According to an embodiment of a semiconductor device, the device includes a semiconductor body with a drift region and neighboring device cells integrated in the semiconductor body. Each device cell includes: a body region arranged between a source region and the drift region; a diode region and a pn junction between the diode region and the drift region; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; and a gate electrode arranged in the trench and dielectrically insulated from the semiconductor body by a gate dielectric. The diode regions together with the drift region act as a JFET, which has a channel region in the drift region between the diode regions. The drift region has a locally increased doping concentration in the channel region of the JFET.

公开(公告)号：US20180076036A1

公开(公告)日：2018-03-15

申请号：US15582940

申请日：2017-05-01

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Markus Kahn ,  Kurt Pekoll ,  Juergen Steinbrenner ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/16 ,  H01L21/324 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L21/0485 ,  H01L21/0217 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/7802

Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.