公开(公告)号：US20180204822A1

公开(公告)日：2018-07-19

申请号：US15871117

申请日：2018-01-15

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/24145 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.

公开(公告)号：US20240371785A1

公开(公告)日：2024-11-07

申请号：US18608969

申请日：2024-03-19

Applicant: Powertech Technology Inc.

Inventor： Ching-Wei Liao ,  Shang-Yu Chang Chien

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10

Abstract: A package structure including a chip, an encapsulant, a first redistribution circuit structure, a second redistribution circuit structure, a conductive member, and a coded structure is provided. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite thereto. The encapsulant covers the chip. The first redistribution circuit structure is disposed on the first encapsulating surface of the encapsulant. The second redistribution circuit structure is disposed on the second encapsulating surface of the encapsulant. The chip is electrically connected to the first redistribution circuit structure or the second redistribution circuit structure. The conductive member penetrates through the encapsulant to be electrically connected to the first redistribution circuit structure and the second redistribution circuit structure. The coded structure is disposed on the second redistribution circuit structure. The coded structure includes a readable coded pattern.

公开(公告)号：US20240274566A1

公开(公告)日：2024-08-15

申请号：US18432081

申请日：2024-02-05

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Chia-Ling Lee

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/19 ,  H01L23/293 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214

Abstract: A package structure includes a chip and a dielectric. The chip includes a chip connector disposed on an active surface of the chip. The dielectric is at least disposed on the active surface of the chip. The chip connector has a top surface and a side surface connected to the top surface. The dielectric does not directly cover part of the side surface close to the top surface.

公开(公告)号：US20240030198A1

公开(公告)日：2024-01-25

申请号：US18204956

申请日：2023-06-02

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ching-Wei Liao ,  Shang-Yu Chang Chien

IPC: H01L25/10 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/105 ,  H01L24/32 ,  H01L24/20 ,  H01L21/568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/32225 ,  H01L2224/214 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L24/96 ,  H01L2224/96 ,  H01L2224/19 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/83005 ,  H01L21/561

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive element, an active chip, an encapsulation layer, another redistribution layer, and a conductive terminal. The conductive element, the active chip, and the encapsulation layer are disposed on the redistribution layer and the encapsulation layer surrounds the conductive element and the active chip. The another redistribution layer is disposed on the conductive element, the active chip and the encapsulation layer and electrically connected to the redistribution layer through the conductive element.

公开(公告)号：US11769763B2

公开(公告)日：2023-09-26

申请号：US17384804

申请日：2021-07-26

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

Abstract: A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area.

公开(公告)号：US20230282587A1

公开(公告)日：2023-09-07

申请号：US17994409

申请日：2022-11-28

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2924/1811 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251

Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.

公开(公告)号：US11637071B2

公开(公告)日：2023-04-25

申请号：US17159152

申请日：2021-01-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/00 ,  H01L25/00

Abstract: A package structure, including a conductive element, multiple dies, a dielectric body, a circuit layer and a patterned insulating layer, is provided. The multiple dies are disposed on the conductive element. A portion of the conductive element surrounds the multiple dies. The dielectric body covers the multiple dies. The circuit layer is disposed on the dielectric body. The circuit layer is electrically connected to the multiple dies. The patterned insulating layer covers the circuit layer. A portion of the patterned insulating layer is disposed between the dies that are adjacent. A manufacturing method of a package structure is also provided.

公开(公告)号：US11309283B2

公开(公告)日：2022-04-19

申请号：US17099801

申请日：2020-11-17

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/538 ,  H01L23/36 ,  H01L23/48

Abstract: A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is electrically connected to the bridge die. The second encapsulant covers the first active die and the second active die. The redistribution circuit structure is electrically connected to the through silicon via die. The through silicon via die is disposed between the first active die and the redistribution circuit structure. A manufacturing method of a packaging structure is also provided.

公开(公告)号：US11251170B2

公开(公告)日：2022-02-15

申请号：US16398246

申请日：2019-04-29

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/053 ,  H01L49/02 ,  H01L23/367 ,  H01L23/552

Abstract: A package structure including a frame structure, a die, an encapsulant, a redistribution structure, and a passive component is provided. The frame structure has a cavity. The die is disposed in the cavity. The encapsulant fills the cavity to encapsulate the die. The redistribution structure is disposed on the encapsulant, the die, and the frame structure. The redistribution structure is electrically coupled to the die. The passive component is disposed on the frame structure and electrically coupled to the redistribution structure through the frame structure. A manufacturing method of a package structure is also provided. The frame structure may provide support, reduce warpage, dissipate heat from the die, act as a shield against electromagnetic interference, and/or provide electrical connection for grounding.

公开(公告)号：US11127699B2

公开(公告)日：2021-09-21

申请号：US16830235

申请日：2020-03-25

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/78 ,  H01L23/552

Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.