公开(公告)号：US20190051625A1

公开(公告)日：2019-02-14

申请号：US16162389

申请日：2018-10-17

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/50 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

公开(公告)号：US10177011B2

公开(公告)日：2019-01-08

申请号：US15603475

申请日：2017-05-24

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A chip packaging method includes forming a first redistribution layer and a first dielectric layer on a first temporary carrier to generate a plurality of first conductive interfaces close to the first temporary carrier, each pair of neighboring first conductive interfaces having a first pitch; forming a second dielectric layer on a first portion of the first redistribution layer and the first dielectric layer so as to cover the first portion of the first redistribution layer and expose a second portion; and forming a second redistribution layer and a third dielectric layer over the second dielectric layer to generate a plurality of second conductive interfaces. A circuitry being formed by at least the first redistribution layer and the second redistribution layer and each pair of neighboring second conductive interfaces has a second pitch larger than the first pitch.

公开(公告)号：US20180374717A1

公开(公告)日：2018-12-27

申请号：US15630972

申请日：2017-06-23

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552

Abstract: An adhesive layer is formed on a semiconductor wafer. The semiconductor wafer is diced to form a plurality of chips. Each of the chips has an adhesive sheet diced from the adhesive layer. Adhesive sheets of the chips are adhered to a carrier. The chips and the carrier are encapsulated by a mold layer. The mold layer is grinded to form a grinded surface. An interconnection structure is formed on the grinded surface. A plurality of semiconductor packages are formed by sawing the mold layer and at least a polyimide layer of the interconnection structure.

公开(公告)号：US10141276B2

公开(公告)日：2018-11-27

申请号：US15599481

申请日：2017-05-19

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

公开(公告)号：US20180076157A1

公开(公告)日：2018-03-15

申请号：US15599481

申请日：2017-05-19

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/10 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/02379 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/12 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

公开(公告)号：US11973037B2

公开(公告)日：2024-04-30

申请号：US17330416

申请日：2021-05-26

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A package structure including a first die, a second die, a dielectric body, a conductive terminal, a circuit layer and a patterned insulating layer is provided. The second die is disposed on the first die. A second active surface of the second die faces a first active surface of the first die. The dielectric body covers the first die. The conductive terminal is disposed on the dielectric body and opposite to the second die. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first die is electrically connected to the conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. The second die is electrically connected to the first die through the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric body.

公开(公告)号：US11670611B2

公开(公告)日：2023-06-06

申请号：US17392369

申请日：2021-08-03

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang-Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L23/488 ,  H01L21/56 ,  H01L21/463 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L21/463 ,  H01L21/56 ,  H01L23/31 ,  H01L23/488 ,  H01L24/11

Abstract: A semiconductor package comprising plurality of bumps and fabricating method thereof. The package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first, the pads formed on a first area of the active surface, each first bump formed on the corresponding pad. The second bumps are formed on the second area, each second bump has first and second different width layers. The encapsulation encapsulates the chip and bumps and is ground to expose the bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased. Therefore, a shallow-grinding or over-grinding does not occur.

公开(公告)号：US11569210B2

公开(公告)日：2023-01-31

申请号：US17342559

申请日：2021-06-09

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538

Abstract: A package structure, including a redistribution circuit layer, a first die, a dielectric body, a first connection circuit, a patterned insulating layer, a second die and a third die, is provided. The first die is disposed on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The dielectric body is disposed on the redistribution circuit layer and covers the first die. The first connection circuit is disposed on the dielectric body and is electrically connected to the redistribution circuit layer. The patterned insulating layer covers the first connection circuit. A portion of the patterned insulating layer is embedded in the dielectric body. The second die is disposed on the dielectric body and is electrically connected to the first connection circuit. The third die is disposed on the redistribution circuit layer, is opposite to the first die, and is electrically connected to the redistribution circuit layer.

公开(公告)号：US11545423B2

公开(公告)日：2023-01-03

申请号：US16952044

申请日：2020-11-18

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/053 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: The disclosure provides a package structure including a redistribution circuit structure, a first circuit board, a second circuit board, a first insulator, multiple conductive terminals, and a package. The redistribution circuit structure has a first connection surface and a second connection surface opposite to each other. The first circuit board and the second circuit board are disposed on the first connection surface and are connected electrically to the redistribution circuit structure. The first insulator is disposed on the first connection surface and covers the first circuit board and the second circuit board. The conductive terminals are connected electrically to and disposed on the first circuit board or the second circuit board. The package is disposed on the second connection surface and is connected electrically to the redistribution circuit structure. A manufacturing method of a package structure is also provided.

公开(公告)号：US20220320052A1

公开(公告)日：2022-10-06

申请号：US17342559

申请日：2021-06-09

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure, including a redistribution circuit layer, a first die, a dielectric body, a first connection circuit, a patterned insulating layer, a second die and a third die, is provided. The first die is disposed on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The dielaectric body is disposed on the redistribution circuit layer and covers the first die. The first connection circuit is disposed on the dielectric body and is electrically connected to the redistribution circuit layer. The patterned insulating layer covers the first connection circuit. A portion of the patterned insulating layer is embedded in the dielectric body. The second die is disposed on the dielectric body and is electrically connected to the first connection circuit. The third die is disposed on the redistribution circuit layer, is opposite to the first die, and is electrically connected to the redistribution circuit layer.