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    SEMICONDUCTOR DEVICE
    71.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130200368A1

    公开(公告)日：2013-08-08

    申请号：US13751783

    申请日：2013-01-28

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO. LTD.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Masakazu MURAKAMI

    IPC: H01L29/786

    CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45

    Abstract: A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used. A transistor is provided which includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer including a hole whose effective mass is 5 or more times, preferably 10 or more times, further preferably 20 or more times that of an electron in the oxide semiconductor layer, a source electrode layer in contact with the oxide semiconductor layer, and a drain electrode layer in contact with the oxide semiconductor layer.

    Abstract translation: 提供具有非常低的截止电流的半导体器件。 使用空穴具有比电子更大的有效质量的氧化物半导体材料。 提供了一种晶体管，其包括栅极电极层，栅极绝缘层，氧化物半导体层，其有效质量为有效质量的5倍以上，优选为10倍以上，更优选为20倍以上 氧化物半导体层，与氧化物半导体层接触的源电极层以及与氧化物半导体层接触的漏电极层。

    STORAGE DEVICE
    73.
    发明申请
    STORAGE DEVICE 有权

    公开(公告)号：US20250159935A1

    公开(公告)日：2025-05-15

    申请号：US18835109

    申请日：2023-01-30

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

    IPC: H10D30/67 ,  G11C5/06 ,  H10B12/00

    Abstract: A storage device that can be miniaturized or highly integrated is provided. A storage device includes a memory cell including a transistor and a capacitor, a first insulator, a second insulator over the first insulator, and a third insulator over the second insulator. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a fourth insulator over the oxide, and a third conductor over the fourth insulator. The second insulator includes a first opening. The fourth insulator and the third conductor are placed in the first opening. The second insulator and the third insulator each include a second opening. The capacitor includes a fourth conductor in contact with the top surface of the second conductor, a fifth insulator over the fourth conductor, and a fifth conductor over the fifth insulator. The second insulator includes a third opening. The first insulator includes a fourth opening. The third insulator includes a fifth opening. The third opening overlaps with at least part of the fourth opening and at least part of the fifth opening in a plan view. A sixth conductor and part of the first conductor are placed inside the third opening. The sixth conductor includes a region in contact with part of the top surface and part of a side surface of the first conductor.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
    75.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250151254A1

    公开(公告)日：2025-05-08

    申请号：US18838009

    申请日：2023-02-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

    IPC: H10B12/00

    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. The second and third transistors share a metal oxide. The capacitor is provided between the first and second transistors. An insulator is provided over an electrode functioning as a source or a drain of the first transistor, and the insulator has an opening reaching the electrode. The capacitor is provided in the opening. One electrode of the capacitor includes, in the opening, a region in contact with the other of the source electrode and the drain electrode of the first transistor. The one electrode of the capacitor includes a region in contact with a gate electrode of the second transistor.

    Storage Device
    76.
    发明申请
    Storage Device 有权

    公开(公告)号：US20250131949A1

    公开(公告)日：2025-04-24

    申请号：US18832322

    申请日：2023-01-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

    IPC: G11C5/10

    Abstract: A novel storage device is provided. A storage device in which N memory layers each including a plurality of memory cells provided in a matrix (Nis an integer greater than or equal to 2) are stacked is provided. A write bit line, a read bit line, and a selection line are provided along a stacking direction of the memory layers, and a write word line and a read word line are provided in the direction orthogonal to the stacking direction of the memory layers. The memory cell includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to the write bit line through a first conductor including a region functioning as one of a source electrode and a drain electrode. The first conductor includes a region where at least one of the top surface, a side surface, and the bottom surface of the first conductor is in contact with the write bit line.

    SEMICONDUCTOR DEVICE
    77.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250069635A1

    公开(公告)日：2025-02-27

    申请号：US18948642

    申请日：2024-11-15

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Hajime KIMURA ,  Atsushi MIYAGUCHI ,  Tatsunori INOUE

    IPC: G11C11/405 ,  G06F12/0893 ,  H01L27/12 ,  H10B12/00

    Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.

    ELECTRONIC DEVICE AND COMMUNICATION SYSTEM
    78.
    发明申请
    ELECTRONIC DEVICE AND COMMUNICATION SYSTEM 有权

    公开(公告)号：US20240385456A1

    公开(公告)日：2024-11-21

    申请号：US18691535

    申请日：2022-09-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Yosuke TSUKAMOTO ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Yoshiaki OIKAWA ,  Kensuke YOSHIZUMI

    IPC: G02B27/01 ,  G02B27/00 ,  G06F1/16 ,  H10K59/12

    Abstract: A multifunctional display apparatus or electronic device is provided. An electronic device that can switch between VR display and AR display is provided. The electronic device includes a first display apparatus, a second display apparatus, a lens, a screen, a wearing tool, and a housing. The wearing tool has a function of fixing the housing to a head. The housing has a function of being transformed into a first mode that closes to block view and a second mode that opens to allow a front side to be viewed. The electronic device has a function of providing a first image displayed on the first display apparatus through the lens and the screen in the first mode, and a function of providing a second image projected to the screen from the second display apparatus in the second mode.

    IMAGING DEVICE AND ELECTRONIC DEVICE
    79.
    发明公开
    IMAGING DEVICE AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240266378A1

    公开(公告)日：2024-08-08

    申请号：US18567132

    申请日：2022-06-06

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Takayuki IKEDA ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

    IPC: H01L27/146 ,  H01L23/00

    CPC classification number: H01L27/14634 ,  H01L24/08 ,  H01L2224/08145

    Abstract: One embodiment of the present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. The imaging device is formed by bonding a plurality of layers or stacks each including a device to each other. A pixel circuit; a memory circuit; and a pixel driver circuit, a driver circuit of the memory circuit, and the like can be provided for a first layer, a second layer, and a third layer, respectively. With such a structure, a small imaging device can be formed. Furthermore, wiring delay or the like can be inhibited by stacking the circuits, so that a high-speed operation can be performed.

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