公开(公告)号：US12046669B2

公开(公告)日：2024-07-23

申请号：US18206620

申请日：2023-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7787

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A gate is disposed on the second III-V compound layer. The gate includes a first P-type III-V compound layer, an undoped III-V compound layer and an N-type III-V compound layer are deposited from bottom to top. The first P-type III-V compound layer, the undoped III-V compound layer, the N-type III-V compound layer and the first III-V compound layer are chemical compounds formed by the same group III element and the same group V element. A drain electrode is disposed at one side of the gate. A drain electrode is disposed at another side of the gate. A gate electrode is disposed directly on the gate.

公开(公告)号：US11990539B2

公开(公告)日：2024-05-21

申请号：US17148526

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.

公开(公告)号：US20240145594A1

公开(公告)日：2024-05-02

申请号：US17993983

申请日：2022-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a gate structure on the STI and the substrate, forming a patterned mask on the STI and the gate structure, performing an etching process to remove part of the STI for forming a first trench adjacent to one side of the gate structure and a second trench adjacent to another side of the gate structure, and then forming a contact etch stop layer (CESL) on the gate structure and into the first trench and the second trench.

公开(公告)号：US20240120416A1

公开(公告)日：2024-04-11

申请号：US18542781

申请日：2023-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a gate dielectric layer on the barrier layer; forming a work function metal layer on the gate dielectric layer; patterning the work function metal layer and the gate dielectric layer; forming a gate electrode on the work function metal layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US20240120398A1

公开(公告)日：2024-04-11

申请号：US17981504

申请日：2022-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: The invention discloses a semiconductor device comprising a first transistor and a second transistor, wherein the first transistor and the first transistor are separated by an air gap. The first transistor includes a first fin structure including a first source, a first drain, and a first channel. The second transistor includes a second fin structure including a second source, a second drain, and a second channel.

公开(公告)号：US20240113215A1

公开(公告)日：2024-04-04

申请号：US17980538

申请日：2022-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/311 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/022 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/66462

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a channel layer on a substrate, forming a first barrier layer on the channel layer, forming a p-type semiconductor layer on the first barrier layer, forming a first patterned passivation layer on the p-type semiconductor layer, and then forming a gate electrode on the first patterned passivation layer. Preferably, the gate electrode includes a first portion adjacent to one side of the first patterned passivation layer and a second portion adjacent to another side of the first patterned passivation layer.

公开(公告)号：US11935788B2

公开(公告)日：2024-03-19

申请号：US17137298

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L23/544

Abstract: A manufacturing method of a semiconductor device includes the following steps. A singulation process is performed to a semiconductor wafer for forming semiconductor dies and includes a first cutting step, a thinning step, and a second cutting step. The first cutting step is configured to form first openings in the semiconductor wafer by etching. A portion of the semiconductor wafer is located between each first opening and a back surface and removed by the thinning step. Each first opening penetrates through the semiconductor wafer after the thinning step. The second cutting step is configured to form second openings. Each second opening penetrates through the semiconductor wafer for separating the semiconductor dies. A semiconductor die includes two first side surfaces opposite to each other and two second side surfaces opposite to each other. A roughness of each first side surface is different from a roughness of each second side surface.

公开(公告)号：US11894434B2

公开(公告)日：2024-02-06

申请号：US17955526

申请日：2022-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer. The first electrode is a conformal layer covers the semiconductor barrier layer and the dielectric layer.

公开(公告)号：US20230369481A1

公开(公告)日：2023-11-16

申请号：US18227329

申请日：2023-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7786 ,  H01L29/6656 ,  H01L29/0649 ,  H01L29/66462

Abstract: A method for forming a high electron mobility transistor includes the steps of forming an epitaxial stack on a substrate, forming a gate structure on the epitaxial stack, forming an insulating layer covering the epitaxial stack and the gate structure, forming a passivation layer on the insulating layer, forming an opening on the gate structure and through the passivation layer to expose the insulating layer, and removing a portion of the insulating layer through the opening to form an air gap between the gate structure and the passivation layer.

公开(公告)号：US11716912B2

公开(公告)日：2023-08-01

申请号：US17483790

申请日：2021-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L27/24 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/826 ,  H10B63/30 ,  H10B63/84 ,  H10N70/066 ,  H10N70/841 ,  H10N70/8833

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.