公开(公告)号：US20200127618A1

公开(公告)日：2020-04-23

申请号：US16664646

申请日：2019-10-25

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F3/195 ,  H03F3/72 ,  H03F3/193 ,  H03F1/56 ,  H03F1/22 ,  H03F1/02 ,  H03H7/38 ,  H04B1/16 ,  H03H11/28 ,  H04B1/00

Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

公开(公告)号：US10381991B1

公开(公告)日：2019-08-13

申请号：US15887816

申请日：2018-02-02

Applicant: pSemi Corporation

Inventor： Miles Sanner ,  Emre Ayranci

IPC: H03F1/22 ,  H03F3/195 ,  H03F1/02 ,  H04B1/16

Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

公开(公告)号：US20190245497A1

公开(公告)日：2019-08-08

申请号：US15887816

申请日：2018-02-02

Applicant: pSemi Corporation

Inventor： Miles Sanner ,  Emre Ayranci

IPC: H03F3/195 ,  H03F1/02

CPC classification number: H03F3/195 ,  H03F1/0211 ,  H03F1/223 ,  H03F1/56 ,  H03F3/193 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/231 ,  H03F2200/249 ,  H03F2200/267 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/396 ,  H03F2200/421 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2203/7209 ,  H04B1/16

Abstract: A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

公开(公告)号：US10326484B1

公开(公告)日：2019-06-18

申请号：US16001871

申请日：2018-06-06

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner ,  Phanindra Yerramilli ,  Kashish Pal

IPC: H04B1/16 ,  H03F3/19

Abstract: A front end module having reduced number of low noise amplifier (LNAs) for receiving various combinations of contiguous aggregation (CA) signals and non-CA signals having different combinations of signals aggregated therein. The FECC can include a broadband LNA and/or a band-switching LNA having at least two modes of operation. An input switch directs a received signal to one of several banks of filters. LNA switches direct the signals from the output of filters within a selected filter bank to particular LNAs. LNAs may be connected by LNA switches to filters in more than one filter bank. The proper mode of operation is selected for the band switching LNA based on the particular frequencies present in the received signal and the filters selected.

公开(公告)号：US20180358938A1

公开(公告)日：2018-12-13

申请号：US15910924

申请日：2018-03-02

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F3/195 ,  H03H7/38 ,  H03H11/28 ,  H03F1/02 ,  H04B1/16 ,  H03F3/72 ,  H03F3/193 ,  H03F1/56 ,  H03F1/22

CPC classification number: H03F3/195 ,  H03F1/0205 ,  H03F1/0261 ,  H03F1/223 ,  H03F1/565 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/7209 ,  H03F2203/7236 ,  H03H7/38 ,  H03H11/28 ,  H04B1/006 ,  H04B1/16

Abstract: A front end circuit architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

公开(公告)号：US20180302039A1

公开(公告)日：2018-10-18

申请号：US15917301

申请日：2018-03-09

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F1/02 ,  H03F3/72 ,  H03F3/195 ,  H03F1/08 ,  H03F3/193 ,  H03F1/56

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

公开(公告)号：US09941849B1

公开(公告)日：2018-04-10

申请号：US15430332

申请日：2017-02-10

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner

IPC: H03F1/22 ,  H03F3/191 ,  H03F3/195 ,  H03F1/02 ,  H03H11/28 ,  H04B1/16

CPC classification number: H03F3/195 ,  H03F1/0205 ,  H03F1/0261 ,  H03F1/223 ,  H03F1/565 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2203/7209 ,  H03F2203/7236 ,  H03H7/38 ,  H03H11/28 ,  H04B1/16

Abstract: An front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the FEM IC allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.