公开(公告)号：US20050253178A1

公开(公告)日：2005-11-17

申请号：US11110918

申请日：2005-04-21

Applicant: Tetsuji Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

Inventor： Tetsuji Yamaguchi ,  Atsuo Isobe ,  Satoru Saito

IPC: H01L21/00 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1259 ,  H01L27/1214

Abstract: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer. In the second annealing, a base metal film absorbs and accumulates heat of the laser irradiation, and a semiconductor layer is supplied with heat of the base metal film in addition to heat of the laser irradiation, thereby enhancing efficiency of the silicide reaction in the source and drain regions.

Abstract translation: 对薄膜集成电路进行自对准处理，而不用担心对玻璃基板的损坏，因此可以实现电路的高速操作。 在玻璃基板上形成贱金属膜，氧化物和基底绝缘膜。 在基底绝缘膜上形成具有侧壁的TFT，并且形成覆盖TFT的金属膜。 在不会引起基板收缩的温度下由RTA等进行退火，在源极和漏极区域形成高阻金属硅化物层。 在除去未反应的金属膜之后，对第二次退火进行激光照射; 因此进行硅化物反应，高阻金属硅化物层变成低电阻金属硅化物层。 在第二退火中，贱金属膜吸收并累积激光照射的热量，并且除了激光照射的热量之外，还向半导体层供应贱金属膜的热量，从而提高源的硅化物反应的效率 和漏区。

公开(公告)号：US20050205869A1

公开(公告)日：2005-09-22

申请号：US11107822

申请日：2005-04-18

Applicant: Shunpei Yamazaki ,  Atsuo Isobe ,  Tamae Takano ,  Hidekazu Miyairi

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Tamae Takano ,  Hidekazu Miyairi

IPC: H01L21/20 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L21/02691 ,  H01L21/02678 ,  H01L21/02683 ,  H01L21/2022 ,  H01L27/12 ,  H01L27/1281

Abstract: To provide devices relating to a manufacturing method for a semiconductor device using a laser crystallization method, which is capable of reducing a cost involved in a design change, preventing a grain boundary from developing in a channel formation region of a TFT, and preventing a remarkable reduction in mobility of the TFT, a decrease in an ON current, and an increase in an OFF current due to the grain boundary and to a semiconductor device formed by using the manufacturing method. In a semiconductor device according to the present invention, among a plurality of TFTs formed on a base film, some TFTs are electrically connected to form logic elements. The plurality of logic elements are used to form a circuit. The base film has a plurality of projective portions having a rectangular or stripe shape. Island-like semiconductor films included in each of the plurality of TFTs are formed between the plurality of projective portions and also, are crystallized by a laser light scanned in a longitudinal direction of the projective portions.

公开(公告)号：US06933527B2

公开(公告)日：2005-08-23

申请号：US10330025

申请日：2002-12-27

Applicant: Atsuo Isobe ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Shunpei Yamazaki ,  Mai Akiba

Inventor： Atsuo Isobe ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Shunpei Yamazaki ,  Mai Akiba

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/104 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L21/02683 ,  H01L21/2022 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675 ,  H01L29/78696

Abstract: It is a problem to provide a semiconductor device production system using a laser crystallization method capable of preventing grain boundaries from forming in a TFT channel region and further preventing conspicuous lowering in TFT mobility due to grain boundaries, on-current decrease or off-current increase. An insulation film is formed on a substrate, and a semiconductor film is formed on the insulation film. Due to this, preferentially formed is a region in the semiconductor film to be concentratedly applied by stress during crystallization with laser light. Specifically, a stripe-formed or rectangular concavo-convex is formed on the semiconductor film. Continuous-oscillation laser light is irradiated along the striped concavo-convex or along a direction of a longer or shorter axis of rectangle.

Abstract translation: 提供一种使用能够防止在TFT沟道区域中形成晶界的激光晶体化方法的半导体器件制造系统的问题，并且进一步防止由于晶界引起的TFT迁移率的明显降低，导通电流降低或截止电流增加 。 在基板上形成绝缘膜，在绝缘膜上形成半导体膜。 由此，优选形成半导体膜中通过激光在结晶期间通过应力集中施加的区域。 具体地，在半导体膜上形成条状或矩形凹凸。 连续振荡激光沿着条纹凹凸或长轴或短轴方向照射。

公开(公告)号：US20050158936A1

公开(公告)日：2005-07-21

申请号：US11064820

申请日：2005-02-25

Applicant: Kiyoshi Kato ,  Toshihiko Saito ,  Atsuo Isobe ,  Toru Takayama ,  Junya Maruyama ,  Yuugo Goto ,  Yumiko Ohno

Inventor： Kiyoshi Kato ,  Toshihiko Saito ,  Atsuo Isobe ,  Toru Takayama ,  Junya Maruyama ,  Yuugo Goto ,  Yumiko Ohno

IPC: H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/78696 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2221/68368

Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device. The present invention relates to a semiconductor device with a plurality of cells each having a plurality of TFTs that have the same channel length direction, in which the plural cells form a plurality of columns along the channel length direction, in which an island-like semiconductor film of each of the plural TFTs is crystallized by laser light running in the channel length direction, in which a channel formation region of the island-like semiconductor film is placed on a depressive portion of a base film that has a rectangular or stripe pattern concave and convex with the channel length direction matching the longitudinal direction of the depressive portion, and in which a plurality of wires for electrically connecting the plural cells with one another are formed between the plural columns.

公开(公告)号：US06911358B2

公开(公告)日：2005-06-28

申请号：US10330019

申请日：2002-12-27

Applicant: Munehiro Azami ,  Chiho Kokubo ,  Aiko Shiga ,  Atsuo Isobe ,  Hiroshi Shibata ,  Shunpei Yamazaki

Inventor： Munehiro Azami ,  Chiho Kokubo ,  Aiko Shiga ,  Atsuo Isobe ,  Hiroshi Shibata ,  Shunpei Yamazaki

IPC: G02F1/1368 ,  G09F9/00 ,  H01L21/20 ,  H01L21/268 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L21/02678 ,  H01L21/02683 ,  H01L21/02691 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78675

Abstract: A method for manufacturing a semiconductor device having steps of forming an amorphous semiconductor on a substrate having an insulating surface; patterning the amorphous semiconductor to form plural first island-like semiconductors; irradiating a linearly condensed laser beam on the plural first island-like semiconductors while relatively scanning the substrate, thus crystallizing the plural first island-like semiconductors; patterning the plural first island-like semiconductors that have been crystallized to form plural second island-like semiconductors; forming plural transistors using the plural second island-like semiconductors; and forming a unit circuit using a predetermined number of the transistors, where the second island-like semiconductors used for the predetermined number of the transistors are formed from the first island-like semiconductors that are different from each other.

Abstract translation: 一种制造半导体器件的方法，具有在具有绝缘表面的衬底上形成非晶半导体的步骤; 图案化非晶半导体以形成多个第一岛状半导体; 在相对扫描基板的同时，在多个第一岛状半导体上照射线性聚集的激光束，从而使多个第一岛状半导体结晶; 图案化已经结晶以形成多个第二岛状半导体的多个第一岛状半导体; 使用多个第二岛状半导体形成多个晶体管; 并且使用预定数量的晶体管形成单位电路，其中用于预定数量的晶体管的第二岛状半导体由彼此不同的第一岛状半导体形成。

公开(公告)号：US06884668B2

公开(公告)日：2005-04-26

申请号：US10370055

申请日：2003-02-21

Applicant: Shunpei Yamazaki ,  Atsuo Isobe ,  Tamae Takano ,  Hidekazu Miyairi

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Tamae Takano ,  Hidekazu Miyairi

IPC: H01L21/20 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L21/00 ,  H01L29/04

CPC classification number: H01L21/02691 ,  H01L21/02678 ,  H01L21/02683 ,  H01L21/2022 ,  H01L27/12 ,  H01L27/1281

Abstract: To provide devices relating to a manufacturing method for a semiconductor device using a laser crystallization method, which is capable of reducing a cost involved in a design change, preventing a grain boundary from developing in a channel formation region of a TFT, and preventing a remarkable reduction in mobility of the TFT, a decrease in an ON current, and an increase in an OFF current due to the grain boundary and to a semiconductor device formed by using the manufacturing method. In a semiconductor device according to the present invention, among a plurality of TFTs formed on a base film, some TFTs are electrically connected to form logic elements. The plurality of logic elements are used to form a circuit. The base film has a plurality of projective portions having a rectangular or stripe shape. Island-like semiconductor films included in each of the plurality of TFTs are formed between the plurality of projective portions and also, are crystallized by a laser light scanned in a longitudinal direction of the projective portions.

Abstract translation: 为了提供与使用激光结晶法的半导体器件的制造方法相关的装置，其能够降低设计变化中涉及的成本，防止晶界在TFT的沟道形成区域中发展，并且防止显着 TFT的迁移率的降低，导通电流的降低以及由于晶界引起的关断电流的增加以及通过使用该制造方法形成的半导体器件。 在根据本发明的半导体器件中，在形成在基膜上的多个TFT中，一些TFT电连接形成逻辑元件。 多个逻辑元件用于形成电路。 基膜具有多个具有矩形或条状的突出部分。 包含在多个TFT中的多个TFT中的岛状半导体膜形成在多个投影部之间，并且通过沿着投影部的纵向扫描的激光而结晶化。

公开(公告)号：US06620658B2

公开(公告)日：2003-09-16

申请号：US10071211

申请日：2002-02-11

Applicant: Atsuo Isobe ,  Toru Takayama ,  Tatsuya Arao ,  Akihiko Koura

Inventor： Atsuo Isobe ,  Toru Takayama ,  Tatsuya Arao ,  Akihiko Koura

IPC: H01L2100

CPC classification number: H01L29/78603 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1259 ,  H01L29/4908 ,  H01L29/66757

Abstract: A gate insulating film of a TFT is formed without increasing a substrate temperature so that a substrate having a low heat resistance such as a plastic substrate can be used. Further, a structure in which an S value of the above TFT is improved and an off leak current is reduced is used to realize the improvement of reliability of a semiconductor device. In the case where the gate insulating film is formed, it is formed by sputtering so that a region having 0.4 atomic % to 1.6 atomic % is present at concentration measurement of hydrogen in the film by an HFS analysis (hydrogen forward scattering analysis). Then, an insulating film is formed thereon by sputtering so that a region having 0.2 atomic % or less is present at concentration measurement of hydrogen in the film by an HFS analysis. When a TFT is manufactured using such a structure of the gate insulating film, there are obtained TFT characteristics such that a subthreshold coefficient is low and a leak current flowing between a gate electrode and a source electrode or a leak current flowing between a gate electrode and a drain electrode is suppressed.

公开(公告)号：US06586766B2

公开(公告)日：2003-07-01

申请号：US10124373

申请日：2002-04-18

Applicant: Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

Inventor： Shunpei Yamazaki ,  Etsuko Fujimoto ,  Atsuo Isobe ,  Toru Takayama ,  Kunihiko Fukuchi

IPC: H01L2904

CPC classification number: H01L27/1237 ,  G02F1/13454 ,  H01L27/1248 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78645

Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.

Abstract translation: 本发明提供一种用于制造在同一基板上具有不同LDD结构的TFT器件和TFT器件的高生产率方法。 具体地说，本发明提供了一种新颖的TFT结构，以及高生产率的制造方法。 使用具有良好耐热性的Ta膜或Ta基膜形成互连，并且互连用保护膜覆盖。 互连可以在高温（400〜700℃）下进行热处理，另外，保护膜用作蚀刻停止体。 在器件的外围驱动电路部分中，具有LDD结构的TFT以自对准工艺设置，其中使用侧壁126和127; 而在其中的像素矩阵部分中，具有LDD结构的TFT被设置在非自对准工艺中，其中使用绝缘体125。

公开(公告)号：US09130044B2

公开(公告)日：2015-09-08

申请号：US13529125

申请日：2012-06-21

Applicant: Yutaka Okazaki ,  Atsuo Isobe

Inventor： Yutaka Okazaki ,  Atsuo Isobe

IPC: H01L29/12 ,  H01L29/786

CPC classification number: H01L29/7869

Abstract: The invention relates to a semiconductor device including an oxide semiconductor layer, a gate electrode overlapping with a channel formation region of the oxide semiconductor layer, and a source electrode or a drain electrode overlapping with a first region of the oxide semiconductor layer, and a second region between the channel formation region and the first region. An upper layer of the second region includes a microvoid. The microvoid is formed by adding nitrogen to the upper layer of the second region. Thus, upper layer of the second region contains lager amount of nitrogen than a lower layer of the second region.

Abstract translation: 本发明涉及包括氧化物半导体层，与氧化物半导体层的沟道形成区重叠的栅电极以及与氧化物半导体层的第一区重叠的源电极或漏电极的半导体器件，以及第二 在通道形成区域和第一区域之间。 第二区域的上层包括微孔。 通过向第二区域的上层添加氮形成微孔。 因此，第二区域的上层比第二区域的下层含有大量的氮。

公开(公告)号：US08847233B2

公开(公告)日：2014-09-30

申请号：US13463092

申请日：2012-05-03

Applicant: Atsuo Isobe ,  Toshinari Sasaki ,  Junichi Koezuka ,  Shunpei Yamazaki

Inventor： Atsuo Isobe ,  Toshinari Sasaki ,  Junichi Koezuka ,  Shunpei Yamazaki

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/108 ,  H01L21/84 ,  H01L49/02 ,  H01L21/425 ,  H01L29/66 ,  H01L29/786 ,  H01L27/115

CPC classification number: H01L29/4238 ,  H01L21/02565 ,  H01L21/265 ,  H01L21/425 ,  H01L21/84 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78693

Abstract: It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.

Abstract translation: 本发明的目的是提供一种抑制短路效应并实现小型化的半导体器件及其制造方法。 在绝缘层中形成沟槽，并且将杂质添加到与沟槽的上端角部接触的氧化物半导体膜，由此形成源极区域和漏极区域。 利用上述结构，可以实现小型化。 此外，利用沟槽，即使当源电极层和漏电极层之间的距离缩短时，也可以适当地抑制沟槽的深度适当地设定短沟道效应。