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公开(公告)号：US20220123771A1
公开(公告)日：2022-04-21
申请号：US17450574
申请日：2021-10-12
Inventor： Gilles MASSON
IPC: H04B1/10
Abstract: This electronic notch filter is able to receive an input signal and deliver a filtered signal having an amplitude, at a cut-off frequency, that is attenuated with respect to that of the input signal.
It comprises a module for integrating the input signal during several successive time windows, each time window starting at a respective initial time instant and having a duration substantially equal to the inverse of the cut-off frequency, the initial temporal time instants of at least two distinct windows being separated by a temporal shift of a value greater than or equal to a predefined reference duration, each integration of the input signal during a respective temporal window resulting in a respective intermediate signal; and a module for summing the intermediate signals coming from the integration module; the filtered signal depending on the sum of said intermediate signals.-
公开(公告)号：US11300518B2
公开(公告)日：2022-04-12
申请号：US16958110
申请日：2018-12-21
Inventor： Emeric Bergmann , Jean-Charles Baritaux , Baptiste Boit , Aline Lecocq , Veronique Rebuffel , Oumar Toure , Mathias Ibert
Abstract: A method for determining the degree of polymerization of a polymer is disclosed, the polymer being contained in a sample (2), the method comprising the following steps: a) illuminating the sample (2) using a laser beam (11) and acquiring (100) a Raman spectrum (S) representative of the polymer; b) identifying (110) a peak of interest (Pi) and determining (120) a position (vi) of the peak of interest in the Raman spectrum; c) on the basis of the position of the peak of interest, using a calibration function (ƒ) to determine a degree of polymerization (DP, DE) of the polymer, the calibration function expressing a variation in the position of the peak of interest as a function of the degree of polymerization of the polymer.
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公开(公告)号：US11289439B2
公开(公告)日：2022-03-29
申请号：US16723394
申请日：2019-12-20
Inventor： Jeannet Bernard
Abstract: A method of fabrication of a semiconducting structure intended to be assembled to a second support by hybridisation. The semiconducting structure comprising an active layer comprising a nitrided semiconductor. The method comprises a step for the formation of at least one first and one second insert and during this step, a nickel layer is formed in contact with the support surface, and a localised physico-chemical etching step of the active layer, a part of the active layer comprising the active region being protected by the nickel layer.
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公开(公告)号：US20220093656A1
公开(公告)日：2022-03-24
申请号：US17477332
申请日：2021-09-16
Inventor： François Deneuville
IPC: H01L27/146
Abstract: An image sensor including a plurality of pixels, each including: a photodetector semiconductor region; a metal region arranged on a first surface of the semiconductor region; a band-pass or band-stop interference filter arranged on a second surface of the semiconductor region opposite to the first surface; and between the semiconductor region and the metal region, an absorbing stack comprising, in the order from the semiconductor region, a dielectric layer, a silicon layer, and a tungsten layer.
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公开(公告)号：US20220093501A1
公开(公告)日：2022-03-24
申请号：US17479472
申请日：2021-09-20
Inventor： Candice THOMAS , Jean CHARBONNIER , Perceval COUDRAIN , Maud VINET
IPC: H01L23/498 , G06N10/00 , H01L39/04 , H01L23/00 , H01L21/768
Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.
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Patent Agency Ranking
公开(公告)号：US20220092397A1
公开(公告)日：2022-03-24
申请号：US17475964
申请日：2021-09-15
Inventor： Vincent LORRAIN , Olivier BICHLER , David BRIAND , Johannes Christian THIELE
Abstract: This electronic calculator comprises a plurality of electronic calculation blocks, each of which is configured to implement one or more respective processing layers of an artificial neural network.
The calculation blocks are of at least two different types among: a first type with fixed topology, fixed operation, and fixed parameters, a second type with fixed topology, fixed operation, and modifiable parameters, and a third type with modifiable topology, modifiable operation, and modifiable parameters. For each processing layer implemented by the respective calculation block, the topology is a connection topology for each artificial neuron; the operation is a type of processing to be performed for each artificial neuron; and the parameters include values able to be determined via training of the neural network.-
公开(公告)号：US20220076868A1
公开(公告)日：2022-03-10
申请号：US17418667
申请日：2019-12-27
Applicant: THALES , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
Inventor： Manuel BIBES , Laurent VILA , Jean-Philippe ATTANE , Paul NOËL , Diogo CASTRO VAZ
Abstract: The present invention relates to an electronic device including an input and an output, the device generating an output voltage when the input of the device is supplied, the device comprising: a conversion unit converting a spin current into a charge current having an amplitude and a sign, a spin current application unit applying a spin current to the conversion unit, a ferroelectric layer, which has a ferroelectric polarization and is arranged such that the ferroelectric polarization controls at least one among the amplitude and the sign of the charge current, and an electric field application unit suitable for applying an electric field to the ferroelectric layer to control the ferroelectric polarization.
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公开(公告)号：US11255926B2
公开(公告)日：2022-02-22
申请号：US16618655
申请日：2018-06-01
Inventor： Aurélie Solignac , Claude Fermon , Myriam Pannetier-Lecoeur , Vincent Trauchessec
Abstract: A system for suppressing low frequency noise of magnetoresistive sensors, includes a device for measuring a magnetic field, the device including at least one magnetoresistive sensor, the magnetoresistive sensor having a first sensitivity at a first operating point and a second sensitivity at a second operating point, the sensitivity at the second operating point being low or zero; a modulator configured to switch the at least one magnetoresistive sensor from the first operating point to the second operating point; and a signal processor for processing the signal derived from the device for measuring a magnetic field.
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公开(公告)号：US20220037538A1
公开(公告)日：2022-02-03
申请号：US17381043
申请日：2021-07-20
Inventor： Julien Buckley
IPC: H01L29/861 , H01L29/20
Abstract: A semiconductor diode, including: a first doped semiconductor region of a first conductivity type; a second doped semiconductor region of a second conductivity type opposite to the first conductivity type, arranged on top of and in contact with the upper surface of the first semiconductor region; a first conductive region arranged on top of and in contact with the upper surface of the second semiconductor region, the first conductive region comprising a through opening opposite a portion of the second semiconductor region; a second conductive region made of a material different from that of the first conductive region, coating the upper surface of the second semiconductor region opposite said opening; a cavity extending through the second conductive region and through the second semiconductor region opposite a portion of said opening; a dielectric region coating the lateral walls and the bottom of the cavity; a third conductive region coating the dielectric region on the lateral walls and at the bottom of the cavity, the third conductive region being further electrically in contact with the first and second conductive regions.
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公开(公告)号：US20220011374A1
公开(公告)日：2022-01-13
申请号：US17305527
申请日：2021-07-09
Inventor： Laurent VINIT , Maxime MONTARU
IPC: G01R31/392 , G01R31/367 , G01R31/3832
Abstract: A method for determining an ageing function of an accumulator, the ageing function representing a variation in the capacity or resistance of the accumulator, as a function of variables representative of the operation of the accumulator, the method including carrying out a plurality of experimental cycles of charging and discharging a test accumulator, each cycle being parameterised by accumulator operating parameters that vary as a function of time during the various cycles; b) during experimental cycles, determining experimental data, including a value of each variable parameter, and determining the capacity or the resistance; c) on the basis of the experimental data resulting from b), determining the ageing function of the accumulator; wherein in step a), the variable parameters include the state of charge and a depth of discharge, such that, following step c), the variables of the ageing function with the state of charge and the depth of discharge.
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