公开(公告)号：US07269699B2

公开(公告)日：2007-09-11

申请号：US10733413

申请日：2003-12-12

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G06F12/00 ,  G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

Abstract translation: 存储器系统和将数据读取和写入到存储器件的方法选择性地在具有数据反转的单个DQS模式中操作，并且以双DQS模式操作。 该装置和方法采用数据选通模式改变装置，用于在第一数据选通模式和第二数据选通模式之间选择性地改变存储装置的操作。

公开(公告)号：US20070134856A1

公开(公告)日：2007-06-14

申请号：US11609374

申请日：2006-12-12

Applicant: Jin JANG ,  Jun-Hyuk CHEON

Inventor： Jin JANG ,  Jun-Hyuk CHEON

IPC: H01L21/84

CPC classification number: H01L29/78678 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66765

Abstract: Disclosed herein is a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor, and more specifically a method for fabricating a reverse-staggered polycrystalline silicon thin film transistor wherein a phosphosilicate-spin-on-glass (P-SOG) is used for a gate insulating film. The method comprises the steps of: forming a buffer layer on an insulating substrate; forming a gate metal pattern on the buffer layer; forming a planarized gate insulating film on the gate metal pattern; depositing an amorphous silicon layer on the gate insulating film; crystallizing the amorphous silicon layer into a polycrystalline silicon layer; forming a n+ or p+ layer on the polycrystalline silicon layer; forming a source/drain metal layer on the n+ or p+ layer; and forming a passivation layer on the source/drain metal layer.

Abstract translation: 本文公开了一种用于制造反向交错多晶硅薄膜晶体管的方法，更具体地说，一种用于制造反向交错多晶硅薄膜晶体管的方法，其中磷硅酸盐旋涂玻璃（P-SOG）用于 栅极绝缘膜。 该方法包括以下步骤：在绝缘基板上形成缓冲层; 在缓冲层上形成栅极金属图案; 在栅极金属图案上形成平坦化的栅极绝缘膜; 在栅极绝缘膜上沉积非晶硅层; 将所述非晶硅层结晶成多晶硅层; 在多晶硅层上形成n +或p +层; 在n +或p +层上形成源极/漏极金属层; 以及在源极/漏极金属层上形成钝化层。

公开(公告)号：US20070115751A1

公开(公告)日：2007-05-24

申请号：US11594807

申请日：2006-11-09

Applicant: Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

Inventor： Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

Abstract translation: 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号中的一个来输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US20070073537A1

公开(公告)日：2007-03-29

申请号：US11472304

申请日：2006-06-22

Applicant: Gil-jin Jang ,  Jeong-su Kim ,  Kwang-cheol Oh

Inventor： Gil-jin Jang ,  Jeong-su Kim ,  Kwang-cheol Oh

IPC: G10L15/20

CPC classification number: G10L25/78

Abstract: An apparatus and method for detecting a voice activity period. The apparatus for detecting a voice activity period includes a domain conversion module that converts an input signal into a frequency domain signal in the unit of a frame obtained by dividing the input signal at predetermined intervals, a subtracted-spectrum-generation module that generates a spectral subtraction signal which is obtained by subtracting a predetermined noise spectrum from the converted frequency domain signal, a modeling module that applies the spectral subtraction signal to a predetermined probability distribution model, and a speech-detection module that determines whether a speech signal is present in a current frame through a probability distribution calculated by the modeling module.

Abstract translation: 一种用于检测语音活动期的装置和方法。 用于检测语音活动期间的装置包括域转换模块，该域转换模块将输入信号转换成以预定间隔划分输入信号所获得的帧为单位的频域信号;产生频谱的减法频谱生成模块 通过从转换的频域信号中减去预定的噪声频谱获得的减法信号，将频谱减法信号应用于预定概率分布模型的建模模块，以及确定语音信号是否存在于语音信号中的语音检测模块 通过由建模模块计算的概率分布的当前帧。

公开(公告)号：US20070069788A1

公开(公告)日：2007-03-29

申请号：US11519252

申请日：2006-09-12

Applicant: Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

Inventor： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

IPC: H03K3/00

CPC classification number: G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356156

Abstract: An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

Abstract translation: 半导体存储器件的输出电路包括第一数据路径，第二数据路径和第三数据路径。 第一数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第二数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第三数据路径锁存第一节点的信号，并传送第一节点的信号以产生输出数据。 因此，包括输出电路的半导体存储器件可以使用将波形管线结构与完整管线结构组合在一起的伪流水线结构化电路以相对较高的频率工作。

公开(公告)号：US20070025164A1

公开(公告)日：2007-02-01

申请号：US11453518

申请日：2006-06-15

Applicant: Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

Inventor： Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

IPC: G11C7/00

CPC classification number: G11C5/145

Abstract: A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final boosting node and a gate node of the transfer transistor, enabled during at least a part of the period the power supply voltage is stepped-up by the multi-boosting unit and performing charge sharing between the final boosting node and the gate node of the transfer transistor.

Abstract translation: 一种用于半导体存储器件的电压产生电路。 电压产生电路包括用于升高电源电压的多升压单元，连接到多升压单元的最终升压节点的输出晶体管和输出节点，以及与最终的电连接电连接的电荷共享元件 所述传输晶体管的升压节点和栅极节点在所述周期的至少一部分期间被使能，所述多个升压单元对所述电源电压进行升压，并且在所述最终升压节点和所述转移的所述栅极节点之间执行电荷共享 晶体管。

公开(公告)号：US20060232521A1

公开(公告)日：2006-10-19

申请号：US11396932

申请日：2006-04-03

Applicant: Jin Jang ,  Jae-Won Choi

Inventor： Jin Jang ,  Jae-Won Choi

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2320/0233 ,  G09G2320/043

Abstract: Disclosed are driving circuit and method which are used in an Organic Light Emitting Diode (OLED), and more specifically to a driving circuit of an organic light emitting diode and a driving method thereof which use a thin film transistor (TFT) as an active device. The driving circuit and method can uniformly produce luminance of the light emitting element because the driving current is produced by compensating the unevenness of threshold voltage of the active device. Further, the variance of the threshold voltage Vth due to deterioration of the transistor produced according as the driving circuit of the OLED is utilized for a long time is also compensated, thereby increasing life of the display device which applies the driving circuit of the OLED.

Abstract translation: 公开了用于有机发光二极管（OLED）的驱动电路和方法，更具体地说，涉及使用薄膜晶体管（TFT）作为有源器件的有机发光二极管的驱动电路及其驱动方法 。 驱动电路和方法可以均匀地产生发光元件的亮度，因为通过补偿有源器件的阈值电压的不均匀性来产生驱动电流。 此外，由于由于OLED的驱动电路而产生的晶体管的劣化导致的阈值电压V Sub的变化很长时间也被补偿，从而延长了显示装置的使用寿命 应用OLED的驱动电路。

公开(公告)号：US07118937B2

公开(公告)日：2006-10-10

申请号：US10882933

申请日：2004-07-01

Applicant: Jin Jang ,  Sung-Hwan Kim ,  Hye-Young Choi

Inventor： Jin Jang ,  Sung-Hwan Kim ,  Hye-Young Choi

IPC: H01I51/40

CPC classification number: H01L27/283 ,  B82Y10/00 ,  B82Y30/00 ,  H01L51/0052 ,  H01L51/0516 ,  H01L51/0545 ,  H01L51/56

Abstract: The present invention relates to a method of selectively depositing an organic semiconductor material and a method of manufacturing an organic semiconductor thin film transistor array. Since the thin film transistor array is formed by locally performing a plasma process on a substrate before depositing an organic semiconductor active layer on the substrate, the organic semiconductor material is deposited on only the organic semiconductor active layer having an island shape. Therefore, it is not necessary to use a shadow mask method or a photolithography method to manufacture an active matrix array. Accordingly, the present invention has advantages in that it is possible to obtain a high resolution thin film transistor array and to prevent characteristics of the thin film transistors in the array from being deteriorated.

Abstract translation: 本发明涉及有选择地沉积有机半导体材料的方法和制造有机半导体薄膜晶体管阵列的方法。 由于薄膜晶体管阵列是通过在衬底上淀积有机半导体有源层之前在衬底上局部地执行等离子体处理而形成的，所以有机半导体材料只沉积在具有岛状的有机半导体有源层上。 因此，不需要使用荫罩法或光刻法来制造有源矩阵阵列。 因此，本发明的优点在于可以获得高分辨率薄膜晶体管阵列，并且防止阵列中的薄膜晶体管的特性劣化。

公开(公告)号：US20060224814A1

公开(公告)日：2006-10-05

申请号：US11358798

申请日：2006-02-21

Applicant: Sung-Hoon Kim ,  Seong-Jin Jang ,  Su-Jin Park

Inventor： Sung-Hoon Kim ,  Seong-Jin Jang ,  Su-Jin Park

IPC: G06F12/06

CPC classification number: G11C7/22

Abstract: A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.

Abstract translation: 半导体存储器件可以包括半导体衬底，衬底上的第一单元存储器件和衬底上的第二单元存储器件。 第一单元存储器件可以被配置为响应于命令接收第一至第N个/或以上数据位和/或向外部设备提供第一至第N个/ 信号，地址信号和时钟信号，以及响应于第一芯片选择信号。 第二单元存储器件可以被配置为通过2N个第（N）个数据位接收（N + 1）个第个和/或提供（N + 1） 响应于命令信号，地址信号和时钟信号，以及响应于第二芯片选择信号，向外部设备提供/ SUP>至2N第数据位。 还讨论了相关方法。

公开(公告)号：US20060146752A1

公开(公告)日：2006-07-06

申请号：US11291892

申请日：2005-12-02

Applicant: Hee-jin Jang ,  Youn-hee Han ,  Xiaoyu Liu

Inventor： Hee-jin Jang ,  Youn-hee Han ,  Xiaoyu Liu

IPC: H04Q7/00 ,  H04L12/56

CPC classification number: H04L63/08 ,  H04L63/062 ,  H04L63/0892 ,  H04W12/06 ,  H04W36/0011 ,  H04W36/0016 ,  H04W80/04 ,  H04W84/12 ,  H04W88/08

Abstract: Disclosed is a method for fast handover in a wireless security data communication environment. The fast handover method for a mobile node connected to a network via an access point to perform a data communication in a wireless communication environment according to the present invention includes: performing an authentication while communicating with an authentication server having registration information about the mobile node via an uncontrolled port of the access point so as to make the mobile node connected to the network; performing a mobile Internet Protocol (IP) registration for binding a Care-of-Address (CoA) to a home agent and a correspondent node (CN) via the access point in parallel with performing the authentication; and opening a control port of the access point and relaying data transceived at the mobile node using the CoA when the authentication and the registration being successfully completed. Accordingly, a fast handover of the mobile node can be supported.

Abstract translation: 公开了一种在无线安全数据通信环境中快速切换的方法。 根据本发明的用于经由接入点连接到网络的移动节点的快速切换方法包括：在与具有关于移动节点的注册信息的认证服务器通信的同时进行认证，所述认证服务器经由 接入点的不受控端口，以使移动节点连接到网络; 执行移动因特网协议（IP）注册，以通过与执行认证并行地经由接入点来绑定归属代理和通信节点（CN）的转交地址（CoA）; 并且当验证和注册成功完成时，使用CoA打开接入点的控制端口并中继在移动节点处收发的数据。 因此，可以支持移动节点的快速切换。