公开(公告)号：US20060163677A1

公开(公告)日：2006-07-27

申请号：US11386644

申请日：2006-03-22

Applicant: Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

Inventor： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC: H01L29/94

CPC classification number: H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

公开(公告)号：US20050266684A1

公开(公告)日：2005-12-01

申请号：US10920482

申请日：2004-08-18

Applicant: Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Kyung-In Choi

Inventor： Sang-Woo Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Kyung-In Choi

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L21/76864

Abstract: A method forming a tungsten contact can include forming a contact hole in an interlayer dielectric layer to expose a portion of an underlying silicon based substrate and to form a side wall of the contact hole. A tungsten silicide layer can be formed on at least on the exposed portion of the substrate. A tungsten nitride layer can be conformally formed on a surface of the interlayer dielectric layer, on the tungsten silicide layer and on the side wall. A contact tungsten layer can be formed on the tungsten nitride layer to fill the contact hole. Related apparatus and contacts are also disclosed.

Abstract translation: 形成钨接触的方法可以包括在层间电介质层中形成接触孔以暴露下面的硅基衬底的一部分并形成接触孔的侧壁。 至少在衬底的暴露部分上可以形成硅化钨层。 氮化钨层可以共形地形成在层间电介质层的表面上，硅化钨层和侧壁上。 可以在氮化钨层上形成接触钨层以填充接触孔。 还公开了相关装置和接触。

公开(公告)号：US20050184394A1

公开(公告)日：2005-08-25

申请号：US11063936

申请日：2005-02-23

Applicant: Sang-woo Lee ,  Gil-heyun Choi ,  Sang-bom Kang ,  Jong-myeong Lee ,  Jin-ho Park

Inventor： Sang-woo Lee ,  Gil-heyun Choi ,  Sang-bom Kang ,  Jong-myeong Lee ,  Jin-ho Park

IPC: H01L21/28 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76846 ,  H01L21/76841 ,  H01L21/76856 ,  H01L21/76877

Abstract: A method of forming a metal wiring in a semiconductor device can include forming an etch stop layer outside a contact hole formed in an insulation layer and avoiding forming the etch stop layer inside the contact hole. A conductive layer can be formed on the etch stop layer outside the contact hole and on an exposed conductive pattern inside the contact hole and on a sidewall of the contact hole and a metal layer can be formed on the conductive layer to fill the contact hole.

Abstract translation: 在半导体器件中形成金属布线的方法可以包括在形成在绝缘层中的接触孔之外形成蚀刻停止层，并避免在接触孔内形成蚀刻停止层。 可以在接触孔外部的蚀刻停止层上形成导电层，并且在接触孔内部和接触孔的侧壁上的暴露的导电图案上形成导电层，并且可以在导电层上形成金属层以填充接触孔。

公开(公告)号：US06602782B2

公开(公告)日：2003-08-05

申请号：US09862937

申请日：2001-05-22

Applicant: Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

Inventor： Myoung-bum Lee ,  Jong-Myeong Lee ,  Byung-hee Kim ,  Gil-heyun Choi

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a metal interconnects include forming an electrically insulating layer having a contact hole therein, on a substrate. A step is also performed to form an electrically conductive seed layer. The seed layer extends on a sidewall of the contact hole and on a portion of an upper surface of the electrically insulating layer extending adjacent the contact hole. The seed layer is sufficiently thick along an upper portion of the sidewall and sufficiently thin along a lower portion of the sidewall that an upper portion of the contact hole is partially constricted by the seed layer and a constricted contact hole is thereby defined. An anti-nucleation layer is deposited on a portion of the seed layer that extends outside the constricted contact hole. The constricted contact hole is used as a mask to inhibit deposition of the anti-nucleation layer adjacent a bottom of the constricted contact hole. A metal liner is then formed on a portion of the electrically conductive seed layer that defines a sidewall of the constricted contact hole. Next, a metal interconnect layer is reflowed into the constricted contact hole to thereby fill and bury the contact hole.

Abstract translation: 形成金属互连的方法包括在基板上形成其中具有接触孔的电绝缘层。 还进行步骤以形成导电种子层。 种子层在接触孔的侧壁上延伸，并且在邻近接触孔延伸的电绝缘层的上表面的一部分上延伸。 种子层沿着侧壁的上部足够厚，并且沿着侧壁的下部足够薄，接触孔的上部被种子层部分地收缩，从而限定了收缩的接触孔。 在种子层的在收缩的接触孔外延伸的部分上沉积抗成核层。 收缩的接触孔用作掩模以抑制邻接于缩小的接触孔的底部的防着色层的沉积。 然后在导电种子层的限定收缩的接触孔的侧壁的部分上形成金属衬垫。 接下来，将金属互连层回流到收缩的接触孔中，从而填充并埋入接触孔。

公开(公告)号：US06586340B2

公开(公告)日：2003-07-01

申请号：US10098029

申请日：2002-03-13

Applicant: Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

Inventor： Jong-myeong Lee ,  Byung-hee Kim ,  Myoung bum Lee ,  Ju-young Yun ,  Gil-heyun Choi

IPC: H01L21302

CPC classification number: H01L21/67167 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/67739 ,  H01L21/76882 ,  H01L21/76888 ,  Y10S438/974

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

公开(公告)号：US09355851B2

公开(公告)日：2016-05-31

申请号：US13588393

申请日：2012-08-17

Applicant: Jong-Won Hong ,  Hei-Seung Kim ,  Kyoung-hee Nam ,  In-sun Park ,  Jong-Myeong Lee

Inventor： Jong-Won Hong ,  Hei-Seung Kim ,  Kyoung-hee Nam ,  In-sun Park ,  Jong-Myeong Lee

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/288 ,  H01L23/532 ,  H01L27/115 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53238 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

Abstract translation: 半导体器件包括填充通过衬底上的绝缘中间层的至少一部分形成并包括铜的沟槽的金属图案，以及金属图案中的包含钽，氮化钽，钛，钛中的至少一种的润湿改善层图案 氮化物，钌，钴和锰。

公开(公告)号：US08969196B2

公开(公告)日：2015-03-03

申请号：US13616910

申请日：2012-09-14

Applicant: Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

Inventor： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/285 ,  H01L23/532 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/10855 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Abstract translation: 半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。 阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层 阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。 互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

公开(公告)号：US08735265B2

公开(公告)日：2014-05-27

申请号：US13082861

申请日：2011-04-08

Applicant: Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

Inventor： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC: H01L21/20

CPC classification number: H01L21/02381 ,  G02B6/13 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02675

Abstract: A method of forming a silicon based optical waveguide can include forming a silicon-on-insulator structure including a non-crystalline silicon portion and a single crystalline silicon portion of an active silicon layer in the structure. The non-crystalline silicon portion can be replaced with an amorphous silicon portion and maintaining the single crystalline silicon portion and the amorphous portion can be crystallized using the single crystalline silicon portion as a seed to form a laterally grown single crystalline silicon portion including the amorphous and single crystalline silicon portions.

Abstract translation: 形成硅基光波导的方法可以包括在该结构中形成包括非晶硅部分和活性硅层的单晶硅部分的绝缘体上硅结构。 可以用非晶硅部分替代非晶硅部分，并且使用单晶硅部分作为种子来保持单晶硅部分和非晶部分可以结晶，以形成横向生长的单晶硅部分，其包括非晶态和 单晶硅部分。

公开(公告)号：US08497207B2

公开(公告)日：2013-07-30

申请号：US12829776

申请日：2010-07-02

Applicant: Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

Inventor： Jong-ho Yun ,  Gil-heyun Choi ,  Jong-myeong Lee

IPC: H01L21/00

CPC classification number: H01L21/76895 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76879

Abstract: A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad.

Abstract translation: 可以减少由于金属接触和插塞之间的未对准而导致金属接触和插塞之间的接触电阻Rc增大的半导体器件，并且可以减少在形成插头的过程中Cu填充过程的困难。 半导体器件包括：衬底，其包括有源区和器件隔离层; 金属接触件，其形成在所述基板上并电连接到所述有源区域; 通过无电镀形成在金属接触件上的着陆垫; 以及形成在所述着陆板上并且经由所述着陆垫电连接到所述金属接触件的插头。

公开(公告)号：US08367533B2

公开(公告)日：2013-02-05

申请号：US13152406

申请日：2011-06-03

Applicant: Jung-Ho Yun ,  Gil-heyun Choi ,  Jong-Myeong Lee

Inventor： Jung-Ho Yun ,  Gil-heyun Choi ,  Jong-Myeong Lee

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823835

Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

Abstract translation: 提供半导体器件及其形成方法。 该方法包括在半导体衬底上形成层间电介质，在层间电介质中形成接触孔以露出半导体衬底，在暴露的半导体衬底上形成包括掺杂剂的金属图案，并进行热处理工艺以使半导体衬底 与金属图案形成金属硅化物图案。 热处理工艺包括将掺杂剂扩散到半导体衬底中。