公开(公告)号：US20100211803A1

公开(公告)日：2010-08-19

申请号：US12758101

申请日：2010-04-12

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G06F12/14

CPC classification number: G11B20/00086 ,  G11B20/0021 ,  G11B2220/2537

Abstract: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.

Abstract translation: 公开了用于将加扰的多值数据写入物理介质并用于从物理介质读取加扰的多值数据的方法和装置。 物理介质可以是光盘。 可以由多值LFSR加扰器执行加扰，并且可以由多值LFSR解扰器执行解扰。 此外，加密的多值数据可以包括同步数据和/或用户数据。 在写入过程中可以使用纠错编码，并且可以在读取过程中使用纠正错误的处理。 此外，公开了用于同步写入物理介质和从物理介质读取的多值数据的方法和装置。 还公开了多值相关方法和装置。

公开(公告)号：US20100085802A1

公开(公告)日：2010-04-08

申请号：US12635307

申请日：2009-12-10

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G11C11/00 ,  H03K19/00 ,  H03K19/173

CPC classification number: G06F7/49 ,  G06F17/5045 ,  G11C11/56 ,  H03K19/0002

Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

Abstract translation: 公开了使用n值大于3的n值可逆逆变器的N值再循环锁存器。 提供使用n值自逆变换器的锁存器; 提供使用n值通用逆变器的锁存器; 并且还提供使用不是自反转或通用的逆变器的锁存器。 闩锁可以使用两个单独控制的门。 它也可以使用一个单独控制的门。 提供了N值锁存器，其中状态由作为物理现象的独立实例的信号表示。 还提供了不使用不存在信号作为状态的锁存器。

公开(公告)号：US20090284620A1

公开(公告)日：2009-11-19

申请号：US12435624

申请日：2009-05-05

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04N5/76

CPC classification number: H04N5/775 ,  H04N5/77 ,  H04N5/772 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/8227 ,  H04N9/8233

Abstract: Methods for storing on a storage or memory medium, and retrieving, and displaying of multiple images in a registered manner, the images have been recorded concurrently. The images may comprise at least 2 video programs. A camera system for recording multiple concurrent images is also disclosed. Lenses and corresponding image sensors are calibrated to have calibrated and associated settings for recording multiple images that are substantially registered images. A registered image may be displayed on a single display. It may also be displayed on multiple displays. A camera for recording and displaying registered multiple images may be part of a mobile phone.

Abstract translation: 用于存储在存储介质上的方法，以及以注册方式检索和显示多个图像的方法已被同时记录。 图像可以包括至少两个视频节目。 还公开了用于记录多个并发图像的相机系统。 镜头和相应的图像传感器被校准以具有用于记录基本上记录的图像的多个图像的校准和相关联的设置。 注册的图像可以显示在单个显示器上。 它也可以显示在多个显示器上。 用于记录和显示注册的多个图像的相机可以是移动电话的一部分。

公开(公告)号：US07580472B2

公开(公告)日：2009-08-25

申请号：US11065836

申请日：2005-02-25

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04L25/49

CPC classification number: H04J13/00 ,  H04J13/10

Abstract: Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection.

Abstract translation: 公开了用于生成三元和多值Gold序列的方法和装置。 还公开了检测三值序列和多值序列的方法。 当序列由基于LFSR的序列发生器生成时，可以由三元或多值LFSR解扰器执行检测。 还公开了可以向指定用户分配附加序列的无线系统。 无线系统还可以向用户设备传送信息，从而实现序列生成和序列检测的方法。

公开(公告)号：US20090146851A1

公开(公告)日：2009-06-11

申请号：US12330255

申请日：2008-12-08

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03M7/00

CPC classification number: G06F7/503

Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

Abstract translation: 使用n状态可逆切换功能和作用于至少2n的第一和第二字的不可逆n状态切换功能来实现n = 2的n状态纹波加法器编码器的方法和装置 状态符号被公开。 还公开了相应的解码方法和装置。 所产生的码字可以是可以通过在对应的纹波加法器解码器中使用相同或不同的n状态切换功能来解码的码字。 Feistel网络和LFSR应用编码和解码。 使用编码和解码方法的系统可以是通信，存储和/或金融系统。

公开(公告)号：US20090138535A1

公开(公告)日：2009-05-28

申请号：US12323070

申请日：2008-11-25

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G06F7/58

CPC classification number: H04L9/0662 ,  G06F7/584 ,  G06F2207/583

Abstract: N-state with n equal or greater than 2 modified Linear Feedback Shift Registers (mLFSRs) having a non-reversible n-state switching function have been disclosed. An mLFSR can also contain a device that implements an n-state logic function of which one input is provided with a signal external to the mLFSR. The mLFSR can be in Fibonacci or in Galois configurations. N-state scramblers and corresponding descramblers applying an mLFSR are provided. N-state coding boxes apply non-reversible switching functions connected to n-state scrambling or descrambling functions. Sequence generators and detectors are also disclosed.

Abstract translation: 已经公开了具有n等于或大于2的具有不可逆n状态切换功能的修正的线性反馈移位寄存器（mLFSR）的N态。 mLFSR还可以包含实现n状态逻辑功能的器件，其中一个输入端提供有一个在mLFSR外部的信号。 mLFSR可以在斐波纳契或Galois配置中。 提供了N态扰频器和应用mLFSR的相应的解扰器。 N态编码框应用连接到n状态加扰或解扰功能的不可逆切换功能。 序列发生器和检测器也被公开。

公开(公告)号：US20090092250A1

公开(公告)日：2009-04-09

申请号：US12273262

申请日：2008-11-18

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04L9/00 ,  H04L9/28

CPC classification number: G06F7/582 ,  H04L9/0662 ,  H04L9/12 ,  H04L2209/12

Abstract: Linear Feedback Shift Registers (LFSRs) based 2p state with p>2 or p≧2 scramblers, descramblers, sequence generators and sequence detectors in binary implementation are provided. An LFSR may apply devices implementing a binary XOR or EQUIVALENT function, a binary shift register and binary inverters and binary state generator, wherein at least an output of one shift register element in a first LFSR is connected to a device implementing a reversible binary logic function is a second LFSR. They may also apply 2p state inverters using binary combinational logic are applied. Memory based binary 2p state inverters are also applied. Non-LFSR based n-state scramblers and descramblers in binary logic are also provided. A method for simple correlation calculation is provided. Communication systems and data storage systems applying the provided LFSR devices are also disclosed.

Abstract translation: 提供了基于二进制执行的p> 2或p> = 2扰频器，解扰器，序列发生器和序列检测器的基于2p状态的线性反馈移位寄存器（LFSR）。 LFSR可以应用实现二进制XOR或等效功能的设备，二进制移位寄存器和二进制反相器和二进制状态发生器，其中第一LFSR中的一个移位寄存器元件的至少一个输出连接到实现可逆二进制逻辑功能的器件 是第二个LFSR。 它们也可以应用二阶组合逻辑应用2p状态逆变器。 基于内存的二进制2p状态转换器也被应用。 还提供了基于非LFSR的n态扰频器和二进制逻辑中的解扰器。 提供了一种简单相关计算的方法。 还公开了应用所提供的LFSR设备的通信系统和数据存储系统。

公开(公告)号：US07487194B2

公开(公告)日：2009-02-03

申请号：US11696261

申请日：2007-04-04

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G06F15/00

CPC classification number: G06F7/582

Abstract: N-valued with n≧2 scramblers, descramblers, sequence generators and sequence detectors operate with Linear Feedback Shift Registers (LFSRs) in Galois configuration. Detectors and descramblers in Fibonacci configuration relate to generators and scramblers with LFSRs in Galois configuration. The content of a shift register in a sequence detector in Galois configuration is calculated. Binary and n-valued scramblers in Galois configuration are matched with corresponding self-synchronizing descramblers with Linear Forward Connected Shift Registers. Systems, including communication systems apply scramblers and descramblers, sequence generators and sequence detectors in Galois configuration.

Abstract translation: N值为n = 2的扰频器，解扰器，序列发生器和序列检测器在Galois配置中与线性反馈移位寄存器（LFSR）一起工作。 Fibonacci配置中的检测器和解扰器涉及Galois配置中的LFSR的发生器和扰频器。 计算Galois配置中的序列检测器中的移位寄存器的内容。 Galois配置中的二进制和n值扰频器与具有线性前向连接移位寄存器的相应自同步解扰器匹配。 包括通信系统的系统在Galois配置中应用加扰器和解扰器，序列发生器和序列检测器。

公开(公告)号：US20080180987A1

公开(公告)日：2008-07-31

申请号：US12061286

申请日：2008-04-02

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G11C11/00

CPC classification number: G06F7/49 ,  G06F17/5045 ,  G11C11/56 ,  H03K19/0002

Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

Abstract translation: 公开了使用n值大于3的n值可逆逆变器的N值再循环锁存器。 提供使用n值自逆变换器的锁存器; 提供使用n值通用逆变器的锁存器; 并且还提供使用不是自反转或通用的逆变器的锁存器。 闩锁可以使用两个单独控制的门。 它也可以使用一个单独控制的门。 提供了N值锁存器，其中状态由作为物理现象的独立实例的信号表示。 还提供了不使用不存在信号作为状态的锁存器。

公开(公告)号：US20070226594A1

公开(公告)日：2007-09-27

申请号：US11566725

申请日：2006-12-05

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03M13/00

CPC classification number: H03M13/23 ,  H03M13/39 ,  H03M13/41

Abstract: The invention relates to error-correcting coding and correct restart of decoding after errors of sequences that are coded by convolutional coders or LFSR based descramblers. The signals can be binary or multi-valued signals. Methods and apparatus to convolutional encode and decode sequences of binary and n-valued symbols are disclosed. The invention further discloses methods and apparatus to identify symbols in error in sequences coded according to methods of the invention. Methods and apparatus to correct these errors are provided. Methods and apparatus to repair errors in a Trellis of received sequences are also provided. Methods and apparatus for n-valued Recursive Systematic Convolutional coders and decoders are disclosed.

Abstract translation: 本发明涉及在由卷积编码器或基于LFSR的解扰器编码的序列的错误之后的纠错编码和纠正重新开始解码。 信号可以是二进制或多值信号。 公开了对二进制和n值符号序列进行卷积编码和解码的方法和装置。 本发明还公开了根据本发明方法编码的序列中错误识别符号的方法和装置。 提供了纠正这些错误的方法和装置。 还提供了修复接收序列网格错误的方法和装置。 公开了n值递归系统卷积编码器和解码器的方法和装置。