公开(公告)号：US20040259300A1

公开(公告)日：2004-12-23

申请号：US10795249

申请日：2004-03-09

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Takuya Futase ,  Tomonori Saeki ,  Mieko Kashi

IPC: C01B007/00

CPC classification number: C23F1/30 ,  H01L21/32134 ,  H01L27/10814 ,  H01L28/55 ,  H01L28/60 ,  Y10S134/902

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

公开(公告)号：US20040257112A1

公开(公告)日：2004-12-23

申请号：US10891219

申请日：2004-07-15

Applicant: Renesas Technology Corp.

Inventor： Hideto Hidaka ,  Masakazu Hirose

IPC: H03K019/0175

CPC classification number: H03K19/00361

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

公开(公告)号：US20040256663A1

公开(公告)日：2004-12-23

申请号：US10867787

申请日：2004-06-16

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Yuji Kihara

IPC: H01L027/10 ,  H01L021/336 ,  H01L029/788 ,  H01L021/331 ,  H01L021/8222

CPC classification number: H01L27/108 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

Abstract: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.

Abstract translation: 存储单元包括用于保存存储的数据及其反相数据的第一和第二数据保持部分。 第一和第二p沟道TFT分别补偿从第一和第二电容器泄漏的电荷。 第一（第二）存取晶体管具有分别连接到第一（第二）字线和第二（第一）节点的第一和第二栅电极。 第一（第二）存取晶体管在第一（第二）字线被去激活的泄漏模式中经由第一（第二）p沟道TFT从第一（第二）p沟道TFT泄漏的电荷放电，而第二（第二） 处于H级。

公开(公告)号：US20040253458A1

公开(公告)日：2004-12-16

申请号：US10890108

申请日：2004-07-14

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takuji Matsumoto ,  Toshiaki Iwamatsu

IPC: B32B009/04

CPC classification number: H01L21/3226 ,  H01L21/76251 ,  H01L21/76259 ,  H01L29/16 ,  Y10T428/265

Abstract: A semiconductor wafer includes an oxide film above a silicon layer, and a porous silicon layer which is located above the oxide film and serves as a gettering layer. Gettering of impurities from a silicon layer is not interrupted by the oxide film since the porous silicon layer is placed above the oxide film. The semiconductor wafer having the structure above can be produced by a bonding method. Bonding strength relative to the oxide film is ensured by placing a growth silicon layer between the oxide film and the porous silicon layer, compared with the case in which the oxide film and the porous silicon layer are directly bonded.

Abstract translation: 半导体晶片包括在硅层上方的氧化物膜和位于氧化物膜上方并用作吸杂层的多孔硅层。 由于多孔硅层位于氧化膜的上方，从硅层中除去杂质不会被氧化膜中断。 具有上述结构的半导体晶片可以通过接合方法制造。 与氧化膜和多孔硅层直接接合的情况相比，通过将生长硅层放置在氧化膜和多孔硅层之间来确保相对于氧化膜的结合强度。

公开(公告)号：US20040251517A1

公开(公告)日：2004-12-16

申请号：US10732517

申请日：2003-12-11

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takashi Nakashima

IPC: H01L027/082

CPC classification number: H01L29/66681 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66674 ,  H01L29/7317 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7816

Abstract: A semiconductor device includes a pnull-silicon substrate, nnull-epitaxial growth layers on the pnull-silicon substrate, a field insulating film at the surface of the nnull-epitaxial growth layer, an npn transistor formed at the nnull-epitaxial growth layer, an pnp transistor formed at the nnull-epitaxial growth layer, a DMOS transistor on the nnull-epitaxial growth layer, and a resistance. The DMOS transistor includes an nnull-diffusion layer forming a source, a p-type diffusion layer forming a back gate region, a lightly doped n-type diffusion layer forming a drain, and a heavily doped nnull-diffusion layer forming the drain.

Abstract translation: 半导体器件包括在硅衬底上的硅衬底，n + - 外延生长层，n +外延生长层表面的场绝缘膜，npn 在n +外延生长层上形成的晶体管，n +外延生长层上形成的pnp晶体管，n +外延生长层上的DMOS晶体管和电阻。 DMOS晶体管包括形成源极的n + - 扩散层，形成背栅区的p型扩散层，形成漏极的轻掺杂n型扩散层和重掺杂n +扩散 层形成漏极。

公开(公告)号：US20040248419A1

公开(公告)日：2004-12-09

申请号：US10701462

申请日：2003-11-06

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Yoshiharu Ono

IPC: H01L021/311

CPC classification number: H01L21/76808 ,  H01L21/31144

Abstract: Above a semiconductor substrate are formed a lower conductive layer, an overcoat, a lower insulating film, an etch stop film, and an upper insulating film. A resist pattern formed on the upper insulating film provides holes partially revealing the surface of the overcoat. A wet treatment is performed to the surface of the upper insulating film and the revealed surface within the holes using an acid containing thinner. An organic polymer material film and an organic anti-reflection film are formed to fill the holes. Using a resist pattern formed over the anti-reflection film, an interconnect trench and a hole are formed in the insulating films and other appropriate layers. A plug is formed in the hole and an interconnect is formed in the interconnect trench. This provides a semiconductor device where deterioration of the resolution of a resist is suppressed and non-uniformity of the applied polymer material is prevented.

Abstract translation: 在半导体衬底上形成下导电层，外涂层，下绝缘膜，蚀刻停止膜和上绝缘膜。 形成在上绝缘膜上的抗蚀剂图案提供部分地露出外涂层的表面的孔。 使用含酸稀释剂对上绝缘膜的表面和孔内露出的表面进行湿处理。 形成有机聚合物材料膜和有机防反射膜以填充孔。 使用形成在抗反射膜上的抗蚀剂图案，在绝缘膜和其它合适的层中形成互连沟槽和孔。 在孔中形成插塞，并且在互连沟槽中形成互连。 这提供了抑制抗蚀剂的分辨率劣化并且防止施加的聚合物材料的不均匀性的半导体器件。

公开(公告)号：US20040245596A1

公开(公告)日：2004-12-09

申请号：US10786081

申请日：2004-02-26

Applicant: Renesas Technology Corp.

Inventor： Tsuyoshi Sugihara

IPC: H01L021/335

CPC classification number: H01L27/11521 ,  H01L21/76224 ,  H01L27/115

Abstract: A semiconductor device having a trench isolation includes a trench formed in a surface of a semiconductor substrate and a buried insulating layer which fills the inside of the trench and has its top surface entirely located above the surface of the semiconductor substrate. A part of the buried insulating layer that protrudes from the surface of the semiconductor substrate has a projecting portion which is located on the surface of the semiconductor substrate and projects outward from a region directly above the trench. The projecting portion has a structure formed of at least two stacked insulating layers. Accordingly, the semiconductor device having the trench isolation can be provided by which a reverse narrow-channel effect can be suppressed and a reliable gate insulating layer can be obtained.

Abstract translation: 具有沟槽隔离的半导体器件包括形成在半导体衬底的表面中的沟槽和填充沟槽内部并且其顶表面完全位于半导体衬底的表面上方的掩埋绝缘层。 从半导体衬底的表面突出的掩埋绝缘层的一部分具有位于半导体衬底的表面上并从沟槽正上方的区域向外突出的突出部分。 突出部分具有由至少两个堆叠的绝缘层形成的结构。 因此，可以提供具有沟槽隔离的半导体器件，通过该半导体器件可以抑制反向窄通道效应并且可以获得可靠的栅极绝缘层。

公开(公告)号：US20040235255A1

公开(公告)日：2004-11-25

申请号：US10730099

申请日：2003-12-09

Applicant: Renesas Technology Corp.

Inventor： Yoshinori Tanaka ,  Katsuyuki Horita ,  Heiji Kobayashi

IPC: H01L021/336

CPC classification number: H01L27/10873 ,  H01L21/26586 ,  H01L27/10817 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle null of the ion implantation, an implant angle is adopted that satisfies the relationship tannull1(W2/T)

Abstract translation: 提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。 在形成氧化硅膜（20）和氮化硅膜（21）的情况下，在对角上方沿Y方向注入p型杂质离子（231,232）。 对于离子注入的注入角α，采用满足tan <-1>（W2 / T）

公开(公告)号：US20040235220A1

公开(公告)日：2004-11-25

申请号：US10687085

申请日：2003-10-17

Applicant: Renesas Technology Corp.

Inventor： Hiroshi Maeda

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L24/28 ,  H01L21/563 ,  H01L23/296 ,  H01L23/5256 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05147

Abstract: A semiconductor chip (15) having a pad (5) covered with a passivation film (7) is prepared, and the passivation film (7) over the pad (5) is selectively removed to expose the pad (5). Next, a polyimide film (11) having an opening (12) for exposing the pad (5) is formed on the passivation film (7). Thereafter, solder bumps (14) are formed on the pad (5), and an underfill resin (17) is filled between an assembly substrate (16) and the semiconductor chip (15) to bond the assembly substrate (16) and semiconductor chip (15) with the solder bumps (14) interposed therebetween.

Abstract translation: 准备具有被钝化膜（7）覆盖的焊盘（5）的半导体芯片（15），并且选择性地去除焊盘（5）上的钝化膜（7）以露出焊盘（5）。 接着，在钝化膜（7）上形成具有露出垫（5）的开口（12）的聚酰亚胺膜（11）。 此后，在焊盘（5）上形成焊料凸块（14），在组装基板（16）和半导体芯片（15）之间填充底部填充树脂（17），以将组装基板（16）和半导体芯片 （15），其间插入有焊料凸块（14）。

公开(公告)号：US20040234413A1

公开(公告)日：2004-11-25

申请号：US10865840

申请日：2004-06-14

Applicant: Renesas Technology Corp

Inventor： Motoaki Sakashita ,  Katsuo Yokota ,  Yasushi Kobayashi ,  Kazumi Anazawa

IPC: B01J008/02

CPC classification number: B01J8/0015 ,  B01J8/0085 ,  B01J8/025 ,  B01J8/0257 ,  B01J2219/185

Abstract: An object of the present invention is to provide a chemical decontamination liquid decomposing system having a catalyst tower which has a mesh filter capable of certainly preventing catalyst from flowing out and a mechanism of pushing-down the catalyst capable of preventing convection of the catalyst caused by decomposition gas. The catalyst tower in accordance with the present invention used for decomposing a chemical decontamination liquid comprises an inlet pipe, a catalyst for decomposing the chemical decontamination liquid, an outlet mesh filter for preventing the catalyst from flowing out, an outlet pipe, a catalyst charging port for charging the catalyst, a catalyst pushing-down mechanism for preventing occurrence of convection of the catalyst caused by a decomposed gas and so on. The outlet mesh filter is arranged so as to closely attached to the inner surface of the catalyst tower and to the inner surface of the catalyst charging port.

Abstract translation: 本发明的目的是提供一种具有催化塔的化学去污液分解系统，该催化塔具有能够有效防止催化剂流出的网状过滤器，并且能够抑制能够防止催化剂对流引起的催化剂的机理 分解气体。 用于分解化学去污液的根据本发明的催化剂塔包括入口管，用于分解化学去污液的催化剂，用于防止催化剂流出的出口网过滤器，出口管，催化剂装料口 用于装载催化剂的催化剂下推机构，用于防止由分解气体等引起的催化剂对流的发生。 出口网过滤器布置成紧密地附着在催化塔的内表面和催化剂装料口的内表面上。