Abstract:
A refresh controlling circuit includes an MRS latch unit configured to output a mask information signal of a bank and a mask information signal of a segment by synchronizing a first address signal and a second address signal with a pulse signal, a bank active control unit configured to output a bank active signal in response to the mask information signal of the bank, and a decoding unit configured to output a row address decoding signal in response to the bank active signal, the mask information signal of the segment, and a third address signal.
Abstract:
An apparatus for transmitting data which includes a management unit that manages network-topology information of clients participating in the P2P service, and an interface unit that provides to a first client a peer list including information of a client having the minimum network distance to the first client, based on the network topology information, when receiving a request for content from the first client.
Abstract:
A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal representing the results of the logical operation. A ready signal generator outputs a strobe ready signal having a predetermined enable period in response to an enabled state of the signal outputted from the detection signal coupler. A strobe signal generator generates a read strobe signal and a page address strobe signal for latch of the page address signals in response to the strobe ready signal. Page address buffers are enabled by the page address strobe signal, and latch the page address signals, thereby buffering the page address signals, a page address decoder which decodes the buffered page address signals respectively outputted from the page address buffers. And, a column selection signal generator outputs column selection signals respectively corresponding to the decoded page address signals in response to the read strobe signal.
Abstract:
Provided are a method and apparatus for relaying streaming data between peers including a first device and a second device in a peer-to-peer (P2P) overlay network. A method of relaying streaming data from the first device to the second device includes determining whether requested streaming data is streaming data that the first device is currently receiving when the first device is requested by the second device to relay streaming data to the second device. Then, the first device assigns a reception bandwidth for receiving the requested streaming data from a source device according to the determination result and receives the requested streaming data using the assigned reception bandwidth to relay the requested streaming data to the second device. Therefore, peers can receive streaming data at a high rate in a P2P network.
Abstract:
A method, apparatus, and system for intermediating contents service. The method includes changing at least part of contents to produce a plurality of pieces of changed key data which are different from each other; and managing trading of the contents between a first and a second device using the produced plurality of pieces of changed key data. The apparatus includes a contents publishing unit which changes at least part of contents, produces a plurality of pieces of changed key data which are different from each other, and stores information on the plurality of pieces of changed key data in a storage unit; and a trade managing unit which manages trading of the contents between a first device and a second device using the stored information on the plurality of pieces of changed key data. The system includes a contents service intermediating server, and first and second devices for trading contents.
Abstract:
An internal power supply voltage generating circuit of semiconductor memory devices configured such that only a predetermined internal power driver is driven but the remaining internal power drivers are not driven, in a standby mode so that the leakage current in standby mode is reduced and the standby current is thus reduced. Furthermore, the leakage current of an internal power driver that does not operate in the standby mode is reduced using a high voltage as a back bias of the internal power driver.
Abstract:
A PSRAM features a mode register set (MRS) for setting a mode register at a combined synchronous and asynchronous mode. The PSRAM having a combined synchronous and asynchronous mode register set includes a MRS, a mode register control unit, a plurality of control signal buffers, an address buffer, a clock buffer, and a synchronous and asynchronous detecting unit. Here, the plurality of control signal buffers, the address buffer and the clock buffers are controlled by a chip selecting signal at an asynchronous mode, and are operated synchronously with respect to an internal clock outputted from the clock buffer regardless of the chip selecting signal at a synchronous mode.