公开(公告)号：US20250070635A1

公开(公告)日：2025-02-27

申请号：US18453776

申请日：2023-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raul BLECIC ,  Syed Wasif MEHDI ,  Pavol BALAZ

IPC: H02M1/00 ,  H03K17/687 ,  H03K19/003

Abstract: A circuit includes a high-side driver having a high-side slew control input, a high-side drive input and a high-side drive output. A low-side driver has a low-side slew control input, a low-side drive input and a low-side drive output. Drive control circuitry has a high-side drive control output, a low-side drive control output, and a slew control output. The high-side drive control output is coupled to the high-side drive input, the low-side drive control output is coupled to the low-side drive input. The slew control output is coupled to at least one of the high-side slew control input and the low-side slew control input, and the drive control circuitry is configured to provide a slew control signal at the slew control output. The high-side and/or low-side driver is configured to modulate a slew rate of a drive signal at a respective drive output thereof based on the slew control signal.

公开(公告)号：US20250070280A1

公开(公告)日：2025-02-27

申请号：US18454652

申请日：2023-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shyam Krishnan VENKATESWARAN ,  Ariton E. XHAFA

IPC: H01M10/42 ,  H01M10/48 ,  H02J7/00

Abstract: In some examples, a battery management system (BMS) includes a set of battery cells and a secondary network node coupled to the set of battery cells. The secondary network node is configured to, responsive to determination by the secondary network node of an exception event, wirelessly transmit a series of periodically repeating reverse wake up data frames to a primary network node. The secondary network node is also configured to, responsive to receipt of a synchronization frame from the primary network node after transmitting the series of reverse wake up data frames, transmit an uplink data frame to the primary network node.

公开(公告)号：US20250069976A1

公开(公告)日：2025-02-27

申请号：US18455163

申请日：2023-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vernon BUCK ,  Katleen Fajardo TIMBOL ,  Jeffrey SOLAS

IPC: H01L23/31 ,  G01N27/22 ,  H01L21/56 ,  H01L23/00 ,  H01L23/24

Abstract: An electronic device includes a substrate and a die having an active surface disposed on the substrate. A sensor is in communication with the active surface of the die and a ring is disposed on the die and encircles the sensor. The ring includes a cylindrical wall and a cap, where the cylindrical wall has an open top and the cap has a partial circular shape that extends beyond each side of the cylindrical wall, A cover is disposed on the cap such that the cover closes off the open top of the ring to form a cavity inside the ring to prevent foreign substance from entering the cavity. A mold compound covers the die and the cover, and abuts an outer surface of the cylindrical wall.

公开(公告)号：US20250068516A1

公开(公告)日：2025-02-27

申请号：US18942874

申请日：2024-11-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siva Srinivas KOTHAMASU

IPC: G06F11/10 ,  G06F13/16 ,  G11C5/04 ,  G11C29/04 ,  G11C29/52

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

公开(公告)号：US20250066526A1

公开(公告)日：2025-02-27

申请号：US18942875

申请日：2024-11-11

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08J5/00 ,  C08K3/04 ,  C08K3/08 ,  C08K7/00 ,  C08L25/06 ,  C08L33/12 ,  G03F1/78

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

公开(公告)号：US12237249B2

公开(公告)日：2025-02-25

申请号：US16175279

申请日：2018-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bernardo Gallegos ,  Madison Koziol

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: A system comprises a substrate. The substrate comprises a lead. The system also comprises a solder barrier formed on the lead. The solder barrier is to contain a solder bump within a solder area on the lead. The system further includes a solder bump in the solder area and a die having an active surface coupled to the solder bump.

公开(公告)号：US12237247B2

公开(公告)日：2025-02-25

申请号：US18527457

申请日：2023-12-04

Applicant: Texas Instruments Incorporated

Inventor： Barry Jon Male ,  Paul Merle Emerson ,  Sandeep Shylaja Krishnan

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

公开(公告)号：US12236177B2

公开(公告)日：2025-02-25

申请号：US17586516

申请日：2022-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lawrence James Gewax ,  Timothy Paul Duryea

IPC: G06F30/33 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F119/02

Abstract: One example includes a method for validating a circuit design. The method includes providing a set of coded rules. Each of the coded rules can define conditions for circuit cells to qualify the circuit design as being radiation-hardened. The method also includes accessing a circuit design netlist associated with the circuit design from a circuit design database. The method also includes evaluating each of the circuit cells in the circuit design netlist with respect to each of the coded rules. The method further includes providing a circuit evaluation report comprising an indication of failure of a set of the circuit cells with respect to one or more of the coded rules in response to the evaluation.

公开(公告)号：US12235168B2

公开(公告)日：2025-02-25

申请号：US18206684

申请日：2023-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nathan Richard Schemm

IPC: G01K15/00 ,  G01K7/01 ,  G01K7/16 ,  G05B11/01 ,  H01L23/34

Abstract: Methods, apparatus, systems and articles of manufacture to trim temperature sensors are disclosed. An example method includes: sampling a first value indicative of a temperature of a first die of a multi-chip module (MCM) with a first temperature sensor, the first die including a first transistor having a channel including a first material; and calibrating a second temperature sensor configured to sample a second value indicative of a temperature of a second die including a second transistor have a second channel including a second material, the calibrating based on the first value.

公开(公告)号：US20250063756A1

公开(公告)日：2025-02-20

申请号：US18938715

申请日：2024-11-06

Applicant: Texas Instruments Incorporated

Inventor： Tatsuya Tominari ,  Nicholas Stephen Dellas ,  Qhalid Fareed

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.