公开(公告)号：US10886303B2

公开(公告)日：2021-01-05

申请号：US15755687

申请日：2017-07-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Pan Li

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1333

Abstract: The application discloses an array substrate, comprising a base, a conductive pattern layer disposed on the base, a transparent electrode layer, and an insulating layer disposed between the conductive pattern layer and the transparent electrode layer, the conductive pattern layer comprises a plurality of first conductive patterns, the transparent electrode layer comprises a plurality of transparent electrodes, each of the transparent electrodes is electrically coupled to a corresponding one of the first conductive patterns through a corresponding via hole in the insulating layer, wherein at a position where at least one via hole is located, a stepped structure is formed between the first conductive pattern corresponding to the via hole and the base and/or the insulating layer such that a groove is formed at an upper surface of the array substrate at a position corresponding to the via hole. The application further discloses a display device.

公开(公告)号：US10564494B2

公开(公告)日：2020-02-18

申请号：US15566610

申请日：2017-03-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Jianbo Xian

IPC: G02F1/1362 ,  G02F1/1345 ,  G09G3/00 ,  G09G3/36 ,  H01L27/02 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

Abstract: An array substrate circuit including an electrostatic discharge circuit for supplying electrostatic discharge to a first signal line for supplying a test signal to the first signal line; wherein, the electrostatic discharge circuit and the test circuit have a shared portion. The array substrate circuit can achieve a lower load of a signal line, and is conducive to achieving a narrow frame panel. An array substrate including the array substrate circuit and a display device are further disclosed.

公开(公告)号：US10347532B2

公开(公告)日：2019-07-09

申请号：US15104551

申请日：2015-10-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaowei Xu ,  Libin Liu ,  Liangjian Li ,  Chunping Long

IPC: H01L21/77 ,  H01L23/552 ,  H01L27/12 ,  H01L27/32

Abstract: The present disclosure provides a Low Temperature Poly Silicon (LTPS) backboard, a method for manufacturing the LTPS, and a light-emitting device. The LTPS backboard includes: a base substrate, and a thin film transistor (TFT) and a light blocking layer that are arranged above the base substrate, wherein the light blocking layer is arranged above the TFT, and the light blocking layer is configured for preventing an irradiation light from irradiating onto the TFT.

公开(公告)号：US10304963B2

公开(公告)日：2019-05-28

申请号：US15083646

申请日：2016-03-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong Lu ,  Dong Li ,  Zheng Liu ,  Shuai Zhang ,  Liang Sun ,  Chunping Long

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/265

Abstract: The embodiments of the present disclosure provide a polysilicon thin film transistor and manufacturing method thereof, an array substrate, and a display panel. The method for manufacturing a polysilicon thin film transistor comprises: forming, on a substrate, a gate, a source and a drain, and an active layer. Forming the active layer comprises: forming a polysilicon layer on the substrate, which comprises a channel region and extension regions; performing ion injection process in the extension regions to form lightly-doped regions close to the channel region and a source region and a drain region; prior to or following the formation of the lightly-doped regions, employing halo ion injection process to form halo regions at the positions of the channel region which are close to the lightly-doped regions.

公开(公告)号：US10304821B2

公开(公告)日：2019-05-28

申请号：US15562853

申请日：2017-03-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Jianbo Xian

IPC: H01L27/02 ,  H01L27/12 ,  H01L27/32 ,  H02H9/00 ,  G09G3/36 ,  G02F1/1362 ,  G02F1/1345

Abstract: An electrostatic discharge (ESD) circuit, an array substrate and a display device are provided. The ESD circuit including a first signal line, a second signal line and a first thin film transistor (TFT), wherein the first TFT includes a plurality of first sub-TFTs; each first sub-TFT includes a first source electrode and a first drain electrode; the first sub-TFTs are sequentially arranged; adjacent first sub-TFT share one first source electrode or first drain electrode; one of the first signal line and the second signal line is electrically connected with the first drain electrode of each first sub-TFT; and the other is electrically connected with the first source electrode of each first sub-TFT.

公开(公告)号：US10203570B2

公开(公告)日：2019-02-12

申请号：US15561185

申请日：2017-04-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes: a plurality of gate lines, a plurality of data lines, and a plurality of common electrodes disposed on a base substrate. The plurality of gate lines are extended in a first direction, the plurality of data lines are extended in a second direction. Each of the common electrodes includes an overlap section which overlaps at least one of the data lines in a direction perpendicular to the base substrate. A gap is provided between the overlap sections of two adjacent common electrodes in the second direction, the two adjacent common electrodes overlap the same data lines in the direction perpendicular to the base substrate. An intersection of the data line and the gate line between the two adjacent common electrodes is located within the gap.

公开(公告)号：US10096663B2

公开(公告)日：2018-10-09

申请号：US14785777

申请日：2015-03-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Xiaoyong Lu ,  Xiaolong Li ,  Chien Hung Liu ,  Chunping Long

IPC: H01L27/12 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises: forming a first conductive thin film (100) on a base substrate (1); and patterning the first conductive thin film (100), to form a pattern of a cathode (11) on a first region (11) of the base substrate (1), and form a pattern of a gate electrode (4) on a second region (12) of the base substrate (1). Complexity and process time of a fabrication process of an array substrate can be reduced, a fabrication process of an organic electroluminescent panel can be simplified, and production cost can be reduced, by forming a cathode layer of a light-emitting diode and a gate electrode layer of a thin film transistor in different regions of the base substrate at the same time by one patterning process.

公开(公告)号：US09947697B2

公开(公告)日：2018-04-17

申请号：US14769891

申请日：2014-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yinan Liang ,  Zheng Liu ,  Zuqiang Wang ,  Xueyan Tian

IPC: H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1288 ,  H01L27/1255 ,  H01L27/3262 ,  H01L2227/323

Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

公开(公告)号：US20170294345A1

公开(公告)日：2017-10-12

申请号：US15512372

申请日：2016-03-03

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaoyong Lu ,  Hongwei Tian ,  Yueping Zuo ,  Xiaowei Xu ,  Wenqing Xu ,  Chunping Long

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/02063 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/67 ,  H01L21/76814

Abstract: Provided are a method and an apparatus for manufacturing a semiconductor device. The method comprises: forming a first wiring layer on a base substrate; forming an interlayer dielectric layer on the first wiring layer, with contact holes being provided in the interlayer dielectric layer; subjecting bottoms of the contact holes to a dry cleaning process; and forming a second wiring layer on the interlayer dielectric layer, wherein the second wiring layer is electrically connected to the first wiring layer via the contact holes.

公开(公告)号：US09761731B2

公开(公告)日：2017-09-12

申请号：US14764307

申请日：2014-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yinan Liang

IPC: H01L27/14 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3065 ,  H01L23/31 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/32

CPC classification number: H01L29/78675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/32139 ,  H01L23/3171 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78633 ,  H01L2227/323

Abstract: A thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The thin film transistor includes a gate electrode, a source electrode, a drain electrode, an active layer and a gate insulation layer. The gate insulation layer is provided above the active layer, the gate, the source electrode and the drain electrode are provided on a same layer above the gate insulation layer, the active layer and the source electrode are connected through a first connection electrode, and the active layer and the drain electrode are connected through a second connection electrode. The thin film transistor can be formed by three times of patterning processes, by which the process time period is shortened, the process yield is improved, and the process cost is reduced, and so on.