公开(公告)号：US07574584B2

公开(公告)日：2009-08-11

申请号：US11186239

申请日：2005-07-21

Applicant: Gerard Chauvel ,  Maija Kuusela

Inventor： Gerard Chauvel ,  Maija Kuusela

IPC: G06F9/00 ,  G06F7/42

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine. For a floating point add instruction, mantissa addition is executed in the integer pipeline and the plurality of operations performed by the hardware state machine includes testing of exponents, testing for overflow and underflow conditions, packing, and rounding detection.

Abstract translation: 在一些实施例中，处理器包括取指令，整数流水线以及与整数流水线分开并与其整体流水线相互作用的硬件状态机。 该指令根据软件部分在整数流水线中执行，部分在硬件状态机中执行。 对于浮点加法指令，在整数流水线中执行尾数加法，并且由硬件状态机执行的多个操作包括指数的测试，溢出和下溢条件的测试，打包和舍入检测。

公开(公告)号：US07555611B2

公开(公告)日：2009-06-30

申请号：US10632076

申请日：2003-07-31

Applicant: Serge Lasserre ,  Maija Kuusela ,  Gerard Chauvel

Inventor： Serge Lasserre ,  Maija Kuusela ,  Gerard Chauvel

IPC: G06F12/00

CPC classification number: G06F12/126 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/502 ,  Y02D10/13

Abstract: A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory preferably is adapted to store two groups of local variables. A first group comprises local variables associated with finished methods and a second group comprises local variables associated with unfinished methods. Further, local variables are saved to, or fetched from, external memory upon a context change based on a threshold value differentiating the first and second groups. The first value may comprise a threshold address or an allocation bit associated with each of a plurality of lines forming the data memory.

Abstract translation: 缓存子系统可以包括多路组关联高速缓存和数据存储器，其保存由存储在寄存器中的地址定义的连续的存储块。 局部变量（例如，Java局部变量）可以存储在数据存储器中。 数据存储器优选地适于存储两组局部变量。 第一组包括与完成的方法相关联的局部变量，第二组包括与未完成方法相关联的局部变量。 此外，基于区分第一和第二组的阈值，在上下文改变时，将局部变量保存到外部存储器或从外部存储器获取。 第一值可以包括与形成数据存储器的多条线中的每一条相关联的阈值地址或分配位。

公开(公告)号：US07506131B2

公开(公告)日：2009-03-17

申请号：US10632215

申请日：2003-07-31

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G06F9/302 ,  G06F9/305

CPC classification number: G06F12/0292 ,  G06F9/541 ,  G06F9/545 ,  G06F2212/401

Abstract: In some embodiments, reformat logic comprises a plurality of registers and translation logic that accesses the registers. The translation logic receives a memory access targeting an application data structure that has a different format than accesses permitted to be provided to a device, which may be a display. The translation logic reformats the request to a format compatible with the device based on values stored in the registers.

Abstract translation: 在一些实施例中，重新格式化逻辑包括访问寄存器的多个寄存器和转换逻辑。 翻译逻辑接收针对应用数据结构的存储器访问，该应用数据结构的格式与允许提供给可能是显示器的设备的访问格式不同。 翻译逻辑基于存储在寄存器中的值将请求重新格式化为与设备兼容的格式。

公开(公告)号：US07493476B2

公开(公告)日：2009-02-17

申请号：US11188827

申请日：2005-07-25

Applicant: Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

Inventor： Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

IPC: G06F9/22

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: A processor is provided that includes decode logic coupled to an instruction cache and a micro-sequence vector table including entries for each bytecode in an instruction set of the processor. The processor also includes a register coupled to the decode logic, wherein the register is dedicated for storage of an immediate operand of a bytecode. The decode logic is configured to obtain a single bytecode from the instruction cache, wherein the single bytecode requires an immediate operand stored in the instruction cache, use the single bytecode to locate an entry corresponding to the bytecode in the micro-sequence vector table, and, when indicated by information in the entry, obtain the immediate operand from the instruction cache and store the immediate operand in the register for use by a micro-sequence that is executed in lieu of the single bytecode.

Abstract translation: 提供了处理器，其包括耦合到指令高速缓存的解码逻辑和包括处理器的指令集中的每个字节码的条目的微序列向量表。 处理器还包括耦合到解码逻辑的寄存器，其中寄存器专用于存储字节码的立即操作数。 解码逻辑被配置为从指令高速缓存获得单个字节码，其中单个字节码需要存储在指令高速缓存中的立即操作数，使用单个字节码来定位与微序列向量表中的字节码相对应的条目，以及 当由条目中的信息指示时，从指令高速缓存中获取立即操作数，并将该立即操作数存储在寄存器中以供代替单字节代码执行的微序列使用。

公开(公告)号：US07434029B2

公开(公告)日：2008-10-07

申请号：US10631120

申请日：2003-07-31

Applicant: Gerard Chauvel ,  Serge Lasserre

Inventor： Gerard Chauvel ,  Serge Lasserre

IPC: G06F9/00

CPC classification number: G06F9/30134 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3879 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/502 ,  Y02D10/13

Abstract: A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the unsupported instruction. If there are less than a threshold number of consecutive supported instructions before the next unsupported instruction, the second processor loads the instructions in the first processor for execution so that the first processor does not fetch the instructions. If there are more than a threshold number of consecutive supported instructions before the next unsupported instruction, the first processor fetches and executes those instructions.

Abstract translation: 系统包括耦合到第二处理器的第一处理器。 第一和第二处理器耦合到存储器。 第一个处理器获取和执行支持的指令，直到检测到不受支持的指令。 第二个处理器执行不支持的指令。 如果在下一个不受支持的指令之前存在小于阈值数量的连续支持的指令，则第二处理器将指令加载到第一处理器中用于执行，使得第一处理器不取指令。 如果在下一个不受支持的指令之前存在超过阈值数量的连续支持的指令，则第一个处理器将获取并执行这些指令。

公开(公告)号：US20080134212A1

公开(公告)日：2008-06-05

申请号：US11741237

申请日：2007-04-27

Applicant: Gerard Chauvel ,  Gilbert Cabillic ,  Jean-Philippe Lesot

Inventor： Gerard Chauvel ,  Gilbert Cabillic ,  Jean-Philippe Lesot

IPC: G06F9/44

CPC classification number: G06F9/4812

Abstract: A method and system for performing a Java interrupt. At least some of the illustrative embodiments are methods comprising executing a thread having a context on a stack based on a first program counter, detecting an interrupt while executing the thread (wherein execution of the thread is temporarily suspended), and executing a method portion to handle the interrupt (wherein the method portion is executed on the stack based on the first program counter, and wherein the context during execution of the method portion is the same as during execution of the thread).

Abstract translation: 一种用于执行Java中断的方法和系统。 至少一些说明性实施例是包括基于第一程序计数器执行在堆栈上具有上下文的线程的方法，在执行线程的同时检测中断（其中线程的执行被暂停），并且执行方法部分 处理中断（其中基于第一程序计数器在堆栈上执行方法部分，并且其中方法部分的执行期间的上下文与执行线程期间相同）。

公开(公告)号：US20080127048A1

公开(公告)日：2008-05-29

申请号：US11560883

申请日：2006-11-17

Applicant: Gerard Chauvel ,  Gilbert Cabillic

Inventor： Gerard Chauvel ,  Gilbert Cabillic

IPC: G06F9/44

CPC classification number: G06F9/451

Abstract: A method and system of accessing display window memory. At least some of the illustrative embodiments are methods comprising abstracting display window memory by way of a first software object, accessing the display window memory by routines of a graphics library executed on a first processor (the accessing by way of the first software object), and displaying a window on a display screen, contents of the window selected at least in part by the routines of the graphics library.

Abstract translation: 访问显示窗口存储器的方法和系统。 至少一些说明性实施例是包括通过第一软件对象抽象显示窗口存储器的方法，通过在第一处理器上执行的图形库（通过第一软件对象的访问）的例程来访问显示窗口存储器， 以及在显示屏幕上显示窗口，至少部分地由所述图形库的例程选择的所述窗口的内容。

公开(公告)号：US07197623B1

公开(公告)日：2007-03-27

申请号：US09606057

申请日：2000-06-28

Applicant: Gerard Chauvel ,  Francis Aussedat ,  Pierre Calippe

Inventor： Gerard Chauvel ,  Francis Aussedat ,  Pierre Calippe

IPC: G06F15/76 ,  H04Q7/20

CPC classification number: G06F9/5044 ,  G06F2209/509

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The Protocol Processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract translation: 旨在与系统的至少一个主处理器相关联的协议处理器，以便执行主处理器不适合的任务。 协议处理器包括一个包括递增寄存器（31）的程序部分（30），连接到递增寄存器（31）以便接收其地址的程序存储器（33），用于接收来自 程序部分（30）的程序存储器（33），用于执行两个周期的指令，以及用于执行指令的数据部分（36）。

公开(公告)号：US07162586B2

公开(公告)日：2007-01-09

申请号：US10631422

申请日：2003-07-31

Applicant: Gerard Chauvel ,  Serge Lasserre

Inventor： Gerard Chauvel ,  Serge Lasserre

IPC: G06F12/08

CPC classification number: G06F9/30134 ,  G06F9/30101 ,  G06F9/30174 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/502

Abstract: A system comprises a main stack, a local data stack and plurality of flags. The main stack comprises a plurality of entries and is located outside a processor's core. The local data stack is coupled to the main stack and is located internal to the processor's core. The local data stack has a plurality of entries that correspond to entries in the main stack. Each flag is associated with a corresponding entry in the local data stack and indicates whether the data in the corresponding local data stack entry is valid. The system performs two instructions. One instruction synchronizes the main stack to the local data stack and invalidates the local data stack, while the other instruction synchronizes the main stack without invalidating the local data stack.

Abstract translation: 系统包括主堆栈，本地数据堆栈和多个标志。 主堆叠包括多个条目并且位于处理器的核心外部。 本地数据堆栈耦合到主栈，并位于处理器核心的内部。 本地数据堆栈具有对应于主栈中的条目的多个条目。 每个标志与本地数据堆栈中的相应条目相关联，并指示对应的本地数据堆栈条目中的数据是否有效。 系统执行两个指令。 一个指令将主堆栈同步到本地数据堆栈，并使本地数据堆栈无效，而另一个指令同步主堆栈而不使本地数据堆栈无效。

公开(公告)号：US20060026565A1

公开(公告)日：2006-02-02

申请号：US11189422

申请日：2005-07-26

Applicant: Gilbert Cabillic ,  Jean-Philippe Lesot ,  Gerard Chauvel

Inventor： Gilbert Cabillic ,  Jean-Philippe Lesot ,  Gerard Chauvel

IPC: G06F9/44

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: Systems, methods, and computer-readable media for interrupt handling in Java are provided. In some illustrative embodiments, a system is provided that includes a Java execution flow class that represents an execution flow context, an execution flow scheduler object including a Java native execution flow activation method, a Java virtual machine, and an interrupt handler class that extends the execution flow class. The execution flow class includes an execution flow execution method and a constructor that creates an execution flow context. The interrupt handler class includes a handler method and an execution flow execution method that overrides the execution flow execution method of the execution flow class. In this system, an interrupt handler object is instantiated using the interrupt handler class, wherein the handler method of the interrupt handler class includes one or more instructions of an interrupt handler for a device interrupt; the constructor creates an execution flow context for the interrupt handler; and the Java virtual machine invokes the execution flow activation method to switch from a currently executing execution flow context to the interrupt handler execution flow context to execute the one or more instructions after the device interrupt is signaled.

Abstract translation: 提供了用于Java中的中断处理的系统，方法和计算机可读介质。 在一些说明性实施例中，提供了一种系统，其包括表示执行流上下文的Java执行流类，包括Java本地执行流激活方法，Java虚拟机和中断处理程序类的执行流调度程序对象， 执行流程类。 执行流类包括执行流执行方法和创建执行流上下文的构造函数。 中断处理程序类包括一个处理程序方法和一个执行流执行方法，该方法将覆盖执行流类的执行流执行方法。 在该系统中，使用中断处理程序类实例化中断处理程序对象，其中中断处理程序类的处理程序方法包括用于器件中断的中断处理程序的一个或多个指令; 构造函数为中断处理程序创建执行流上下文; 并且Java虚拟机调用执行流激活方法以从当前执行的执行流程上下文切换到中断处理程序执行流程上下文，以便在发出设备中断之后执行一个或多个指令。