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    Multiple circuits coupled to an interface
    82.
    发明授权
    Multiple circuits coupled to an interface 有权

    公开(公告)号：US11613117B2

    公开(公告)日：2023-03-28

    申请号：US16956331

    申请日：2019-02-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： James Michael Gardner ,  Scott A. Linn ,  Michael W. Cumbie

    IPC: B41J2/045

    Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an interface, a first sensor, a second sensor, and control logic. The interface is to connect to a single contact pad of a host print apparatus. The first sensor is of a first type and is coupled to the interface. The second sensor is of a second type and is coupled to the interface. The second type is different from the first type. The control logic enables the first sensor or the second sensor to provide an enabled sensor. A voltage bias or a current bias applied to the interface generates a sensed current or a sensed voltage, respectively, on the interface indicating the state of the enabled sensor.

    Communicating print component
    83.
    发明授权
    Communicating print component 有权

    公开(公告)号：US11529805B2

    公开(公告)日：2022-12-20

    申请号：US16956707

    申请日：2019-02-06

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Scott A. Linn ,  James Michael Gardner

    IPC: B41J2/045 ,  G11C13/00

    Abstract: An integrated circuit for a print component including a number of memory bits. The integrated circuit may include a selection circuit to select at least one memory bit of the number of memory bits and fire actuators of a fire pulse group. The integrated circuit may include a memory voltage regulator to provide a write voltage to the at least one memory bit of the number of memory bits.

    Print component with memory circuit
    84.
    发明授权
    Print component with memory circuit 有权

    公开(公告)号：US11491782B2

    公开(公告)日：2022-11-08

    申请号：US16768541

    申请日：2019-07-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Boon Bing Ng ,  James Michael Gardner ,  Scott A. Linn

    IPC: B41J2/045 ,  G06F3/12 ,  G06F13/16 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

    Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

    Pulldown devices
    88.
    发明授权
    Pulldown devices 有权

    公开(公告)号：US11413861B2

    公开(公告)日：2022-08-16

    申请号：US16768059

    申请日：2019-02-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： James Michael Gardner ,  John Rossi ,  Scott A. Linn

    IPC: B41J2/045

    Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of contact pads, a plurality of pulldown devices, and control logic. The plurality of contact pads include a first contact pad and a second contact pad. Each of the pulldown devices is electrically coupled to a corresponding contact pad. The control logic enables at least a portion of the pulldown devices in response to both a logic low signal on the first contact pad and a logic low signal on the second contact pad.

    Identifying random bits in control data packets
    89.
    发明授权
    Identifying random bits in control data packets 有权

    公开(公告)号：US11407218B2

    公开(公告)日：2022-08-09

    申请号：US16769396

    申请日：2019-02-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： John Rossi ,  Scott A. Linn ,  James Michael Gardner ,  Erik D. Ness

    IPC: B41J2/045 ,  G06F3/12

    Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

    Print component with memory array using intermittent clock signal
    90.
    发明授权
    Print component with memory array using intermittent clock signal 有权

    公开(公告)号：US11364719B2

    公开(公告)日：2022-06-21

    申请号：US16767914

    申请日：2019-02-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： James Michael Gardner ,  Scott A. Linn ,  Michael W. Cumbie

    IPC: B41J2/045

    Abstract: A print component includes a plurality of data pads, a clock pad to receive an intermittent clock signal, and a plurality of actuator groups each corresponding to a different liquid type and to a different one of the data pads. Each actuator group includes a plurality of configuration functions, an array of fluid actuators, and an array of memory elements including a first portion corresponding to the plurality of configuration functions and a second portion corresponding to the array of fluid actuators. Each time the intermittent clock signal is present on the clock pad, the array of memory elements to serially load a segment of data bits from the corresponding data pad, including loading a first portion of data bits into the first portion of memory elements, and loading a second portion of data bits into the second portion of memory elements.

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