公开(公告)号：US11637687B2

公开(公告)日：2023-04-25

申请号：US16723743

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Ned Smith ,  Francesc Guim Bernat ,  Sanjay Bakshi ,  Paul O'Neill ,  Ben McCahill ,  Brian A. Keating ,  Adrian Hoban ,  Kapil Sood ,  Mona Vij ,  Nilesh Jain ,  Rajesh Poornachandran ,  Trevor Cooper ,  Kshitij A. Doshi ,  Marcin Spoczynski

IPC: H04L29/06 ,  H04L9/00 ,  G06F16/28 ,  H04L9/06

Abstract: Methods, apparatus, systems and articles of manufacture to determine provenance for data supply chains are disclosed. Example instructions cause a machine to at least, in response to data being generated, generate a local data object and object metadata corresponding to the data; hash the local data object; generate a hash of a label of the local data object; generate a hierarchical data structure for the data including the hash of the local data object and the hash of the label of the local data object; generate a data supply chain object including the hierarchical data structure; and transmit the data and the data supply chain object to a device that requested access to the data.

公开(公告)号：US20220350679A1

公开(公告)日：2022-11-03

申请号：US17867506

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi

IPC: G06F9/54 ,  G06F9/50

Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.

公开(公告)号：US20220261661A1

公开(公告)日：2022-08-18

申请号：US17625946

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Ehsan Hosseinzadeh Khaligh ,  Michael Whitney ,  Nathaniel Sema ,  Kshitij A. Doshi

IPC: G06N5/02 ,  G06Q10/06

Abstract: Methods, apparatus, systems and articles of manufacture to improve job scheduling efficiency are disclosed. An example apparatus includes a feature generator to import default values of features corresponding to a first model type, a label trainer to train labels corresponding to the first model type, and a model evaluator to determine an accuracy metric of the first model type based on a first prediction corresponding to the default features, and update the features from the default values to updated values when the accuracy metric does not satisfy an accuracy threshold.

公开(公告)号：US11379264B2

公开(公告)日：2022-07-05

申请号：US16384554

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Felipe Pastor Beneyto ,  Kshitij A. Doshi ,  Timothy Verrall ,  Suraj Prabhakaran

IPC: G06F9/48 ,  G06F1/3296 ,  G06F1/20 ,  G06F9/50 ,  G06F1/3206 ,  G06F1/30 ,  G06F1/3234

Abstract: Some examples provide for uninterruptible power supply form (UPS) resources and non-UPS resources to be offered in a composite node for customers to use. For a workload run on the composite node, monitoring of non-UPS resource power availability, resource temperature, and/or cooling facilities can take place. In the event, a non-UPS resource experiences a power outage or reduction in available power, temperature that is at or above a threshold level, and/or cooling facility outage, monitoring of performance of a workload executing on the non-UPS resource can take place. If the performance is acceptable and the power available to the non-UPS resource exceeds a threshold level, the supplied power can be reduced. If the performance experiences excessive levels of errors or slows unacceptably, the workload can be migrated to another non-UPS or UPS compliant resource.

公开(公告)号：US11354127B2

公开(公告)日：2022-06-07

申请号：US16927352

申请日：2020-07-13

Applicant: Intel Corporation

Inventor： Harshad S. Sane ,  Anup Mohan ,  Kshitij A. Doshi ,  Mark A. Schmisseur

IPC: G06F9/30 ,  G06F12/0808 ,  G06F9/38 ,  G06F12/126 ,  G06F12/0888 ,  G06F12/0862

Abstract: A computing system includes a memory controller having a plurality of bypass parameters set by a software program, a thresholds matrix to store threshold values selectable by the plurality of bypass parameters, and a bypass function to determine whether a first cache line is to be displaced with a second cache line in a first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of a processor core and the cache from a second memory.

公开(公告)号：US20210271733A1

公开(公告)日：2021-09-02

申请号：US17156119

申请日：2021-01-22

Applicant: Intel Corporation

Inventor： Dmitry Y. Babokin ,  Kshitij A. Doshi ,  Vadim Sukhomlinov

IPC: G06F17/16 ,  G06F7/544 ,  G06F9/30

Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

公开(公告)号：US11044210B2

公开(公告)日：2021-06-22

申请号：US16895539

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez

IPC: H04L12/933 ,  H04L29/10

Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.

公开(公告)号：US11036642B2

公开(公告)日：2021-06-15

申请号：US16396576

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Dimitrios Ziakas ,  Mark A. Schmisseur ,  Kshitij A. Doshi ,  Kimberly A. Malone

IPC: G06F9/50 ,  G06F12/0888 ,  G06F12/1027 ,  G06N3/04 ,  G06F12/06

Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.

公开(公告)号：US10929504B2

公开(公告)日：2021-02-23

申请号：US16691327

申请日：2019-11-21

Applicant: Intel Corporation

Inventor： Dmitry Y. Babokin ,  Kshitij A. Doshi ,  Vadim Sukhomlinov

IPC: G06F17/16 ,  G06F7/544 ,  G06F9/30

Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

公开(公告)号：US10860390B2

公开(公告)日：2020-12-08

申请号：US15636119

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi

IPC: G06F3/00 ,  G06F9/54 ,  G06F9/50

Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.