公开(公告)号：US09577073B2

公开(公告)日：2017-02-21

申请号：US14567504

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L21/324 ,  H01L21/04 ,  H01L21/02 ,  H01L21/311 ,  H01L29/16

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.

Abstract translation: 一种碳化硅半导体衬底，其具有多个第一掺杂区域，该第一掺杂区域在主表面之间彼此横向间隔开，并且形成从主表面延伸至位于第一掺杂区域之上的第三掺杂区域的第二掺杂区域 。 形成从主表面延伸到第一掺杂区的第四掺杂区。 形成具有布置在一个第一掺杂区域的一部分上的底部的栅极沟槽。 将高温步骤施加到衬底上，以便沿着沟槽的侧壁重新排列碳化硅原子，并在栅极沟槽中形成圆角。 去除在离开衬底的高温步骤期间沿着栅极沟槽的侧壁形成的表面层。

公开(公告)号：US20160260829A1

公开(公告)日：2016-09-08

申请号：US15057704

申请日：2016-03-01

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Romain Esteve ,  Dethard Peters ,  Roland Rupp ,  Ralf Siemieniec

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/04 ,  H01L29/417

CPC classification number: H01L29/7804 ,  H01L27/0629 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/401 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

Abstract translation: 半导体器件包括从第一表面延伸到半导体本体的沟槽结构。 沟槽结构包括分别延伸穿过栅极结构的栅极结构和接触结构。 晶体管台面位于沟槽结构之间。 每个晶体管台面包括形成具有漂移结构的第一pn结的主体区和与源区的第二pn结。 与接触结构中的一个直接邻接的二极管区域分别与漂移结构形成第三pn结。

公开(公告)号：US20160260798A1

公开(公告)日：2016-09-08

申请号：US15057669

申请日：2016-03-01

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/861 ,  H01L29/739 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/045 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/02667 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7813 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body with a first main crystal direction parallel to a horizontal plane. Longitudinal axes of trench gate structures are tilted to the first main crystal direction by a tilt angle of at least 2 degree and at most 30 degree in the horizontal plane. Mesa portions are between neighboring trench gate structures. First sidewall sections of first mesa sidewalls are main crystal planes parallel to the first main crystal direction. Second sidewall sections tilted to the first sidewall sections connect the first sidewall sections.

Abstract translation: 半导体器件包括具有平行于水平面的第一主晶体方向的半导体本体。 沟槽栅结构的纵轴在水平面上倾斜至第二主晶体方向至少2度至多30度的倾斜角。 台面部分在相邻的沟槽栅极结构之间。 第一台面侧壁的第一侧壁部分是与第一主晶体方向平行的主晶面。 倾斜到第一侧壁部分的第二侧壁部分连接第一侧壁部分。

公开(公告)号：US20160260709A1

公开(公告)日：2016-09-08

申请号：US15053117

申请日：2016-02-25

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L27/0664 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

Abstract: A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.

Abstract translation: 半导体器件包括具有六方晶格的半导体本体中的沟槽栅极结构。 第一表面的平均表面平面以离轴角倾斜至<1-100>晶体方向，其中离轴角的绝对值在2度至12度的范围内。 沟槽栅极结构沿<1-100>晶体方向延伸。 相邻沟槽栅结构之间的半导体本体的部分形成晶体管台面。 晶体管台面的侧壁偏离平均面平面的法线不超过5度。