公开(公告)号：US09170813B2

公开(公告)日：2015-10-27

申请号：US13763596

申请日：2013-02-08

Applicant: Intel Corporation

Inventor： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC: G06F7/50 ,  G06F9/30 ,  G06F7/02

CPC classification number: G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US12282773B2

公开(公告)日：2025-04-22

申请号：US18534012

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Menachem Adelman ,  Robert Valentine ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Dan Baum ,  Alexander F. Heinecke ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil ,  Raanan Sade

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US12277419B2

公开(公告)日：2025-04-15

申请号：US17134046

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Alexander F. Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Menachem Adelman ,  Christopher J. Hughes ,  Evangelos Georganas ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30

Abstract: Systems, methods, and apparatuses relating to instructions to convert 16-bit floating-point formats are described. In one embodiment, a processor includes fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a source vector comprising N plurality of 16-bit half-precision floating-point elements, and a destination vector to store N plurality of 16-bit bfloat floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the source vector from 16-bit half-precision floating-point format to 16-bit bfloat floating-point format and store each converted element into a corresponding location of the destination vector, decode circuitry to decode the fetched single instruction into a decoded single instruction, and the execution circuitry to respond to the decoded single instruction as specified by the opcode.

公开(公告)号：US20250117218A1

公开(公告)日：2025-04-10

申请号：US18927097

申请日：2024-10-25

Applicant: Intel Corporation

Inventor： Alexander Heinecke ,  Naveen Mellempudi ,  Robert Valentine ,  Mark Charney ,  Christopher Hughes ,  Evangelos Georganas ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.

公开(公告)号：US12260213B2

公开(公告)日：2025-03-25

申请号：US17548214

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  Mark J. Charney ,  Barukh Ziv ,  Alexander Heinecke ,  Milind Girkar ,  Simon Rubanovich

IPC: G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

公开(公告)号：US12182571B2

公开(公告)日：2024-12-31

申请号：US18100194

申请日：2023-01-23

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Menachem Adelman ,  Milind B. Girkar ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Stanislav Shwartsman ,  Dan Baum ,  Igor Yanover ,  Alexander F. Heinecke ,  Barukh Ziv ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil ,  Raanan Sade

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US12106100B2

公开(公告)日：2024-10-01

申请号：US16487421

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Bret L. Toll ,  Raanan Sade ,  Igor Yanover ,  Yuri Gebil ,  Rinat Rappoport ,  Stanislav Shwartsman ,  Menachem Adelman ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US20240248720A1

公开(公告)日：2024-07-25

申请号：US18627907

申请日：2024-04-05

Applicant: Intel Corporation

Inventor： Alexander Heinecke ,  Naveen Mellempudi ,  Robert Valentine ,  Mark Charney ,  Christopher Hughes ,  Evangelos Georganas ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F7/499 ,  H03M7/24

CPC classification number: G06F9/30145 ,  G06F7/49947 ,  G06F9/30025 ,  G06F9/30036 ,  H03M7/24

Abstract: Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.

公开(公告)号：US20240143328A1

公开(公告)日：2024-05-02

申请号：US18386407

申请日：2023-11-02

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30036 ,  G06F9/30043

Abstract: Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.

公开(公告)号：US20240143325A1

公开(公告)日：2024-05-02

申请号：US18386771

申请日：2023-11-03

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F9/30101 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address, and execution circuitry to execute the decoded instruction to store configuration information about usage of storage for two-dimensional data structures at the memory address.