公开(公告)号：US11132044B2

公开(公告)日：2021-09-28

申请号：US16406779

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F1/3206 ,  G06F12/06 ,  G06F12/02 ,  G06F1/3296

Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.

公开(公告)号：US11074989B2

公开(公告)日：2021-07-27

申请号：US16079737

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulachet Tanpairoj ,  John Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/00

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US10950310B2

公开(公告)日：2021-03-16

申请号：US16727472

申请日：2019-12-26

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US10931307B2

公开(公告)日：2021-02-23

申请号：US16235171

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ting Luo

IPC: H03M13/11 ,  G06F11/10

Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.

公开(公告)号：US10915395B2

公开(公告)日：2021-02-09

申请号：US16193171

申请日：2018-11-16

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Xiangang Luo ,  Renato Padilla, Jr. ,  Gary F. Besinga ,  Sampath Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.

公开(公告)号：US20210012851A1

公开(公告)日：2021-01-14

申请号：US16079737

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulache Tanpairoj ,  John Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/20 ,  G11C29/14 ,  G11C29/00

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US20200327934A1

公开(公告)日：2020-10-15

申请号：US16915537

申请日：2020-06-29

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Ting Luo

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

公开(公告)号：US20200159447A1

公开(公告)日：2020-05-21

申请号：US16193171

申请日：2018-11-16

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Xiangang Luo ,  Renato Padilla, JR. ,  Gary F. Besinga ,  Sampath Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C16/26 ,  G11C16/34

Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.

公开(公告)号：US10586602B2

公开(公告)日：2020-03-10

申请号：US16436567

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C29/02 ,  G11C16/24 ,  G11C16/08

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20200043555A1

公开(公告)日：2020-02-06

申请号：US16601275

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Jung Sheng Hoei ,  Harish Reddy Singidi ,  Ting Luo ,  Ankit Vinod Vashi

IPC: G11C16/10 ,  G11C7/04 ,  G11C16/34

Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.