公开(公告)号：US11127699B2

公开(公告)日：2021-09-21

申请号：US16830235

申请日：2020-03-25

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/78 ,  H01L23/552

Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US20210202368A1

公开(公告)日：2021-07-01

申请号：US17080859

申请日：2020-10-27

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US10978408B2

公开(公告)日：2021-04-13

申请号：US16001953

申请日：2018-06-07

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

Abstract: A package structure including at least one semiconductor chip, an insulating encapsulant, a conductive frame, a supporting frame, a conductive layer and a redistribution layer is provided. The at least one semiconductor chip has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the at least one semiconductor chip. The conductive frame is surrounding the insulating encapsulant. The supporting frame is surrounding the conductive frame. The conductive layer is disposed on the backside surface of the semiconductor chip. The redistribution layer is disposed on and electrically connected to the active surface of the semiconductor chip.

公开(公告)号：US10950593B2

公开(公告)日：2021-03-16

申请号：US16114251

申请日：2018-08-28

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L21/768 ,  H01L23/522

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

公开(公告)号：US20200343184A1

公开(公告)日：2020-10-29

申请号：US16392559

申请日：2019-04-23

Applicant: Powertech Technology Inc.

Inventor： Hiroyuki Fujishima ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package including a die stack, an insulating encapsulation encapsulating the die stack, a first redistribution layer (RDL) and a second RDL disposed on two opposite sides of the insulating encapsulation, and a through insulating via disposed aside the die stack and extending through the insulating encapsulation to be electrically connected to the first RDL and the second RDL. The die stack includes a first die and a second die stacked upon one another and electrically connected to the first die. The second die includes a through semiconductor via disposed therein. One of the first die and the second die includes conductive features having different thicknesses. The second RDL is connected to the through semiconductor via of the second die. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US20200328497A1

公开(公告)日：2020-10-15

申请号：US16562442

申请日：2019-09-06

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01Q1/22 ,  H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US10796931B2

公开(公告)日：2020-10-06

申请号：US16724387

申请日：2019-12-23

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.

公开(公告)号：US20200126815A1

公开(公告)日：2020-04-23

申请号：US16724387

申请日：2019-12-23

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.

公开(公告)号：US20200075510A1

公开(公告)日：2020-03-05

申请号：US16116915

申请日：2018-08-30

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L49/02 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: A semiconductor package including a semiconductor die, an insulating encapsulant, a passive component, such as a thin film capacitor, and a redistribution structure is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The insulating encapsulant encapsulates the semiconductor die and exposes the active surface of the semiconductor die. The passive component is disposed on the active surface of the semiconductor die. The redistribution structure is disposed on the active surface of the semiconductor die electrically connected to the conductive pads of the semiconductor die and the passive component. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US10515936B1

公开(公告)日：2019-12-24

申请号：US16016672

申请日：2018-06-25

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L25/16 ,  H01L21/3105

Abstract: A package structure includes a first redistribution structure, a die, a plurality of conductive sheets, a plurality of conductive balls, and a first encapsulant. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die has a plurality of connection pads electrically connected to the first surface of the first redistribution structure. The conductive sheets are electrically connected to the first surface of the first redistribution structure. The conductive balls are correspondingly disposed on the conductive sheets and are electrically coupled to the first surface of the first redistribution structure through the conductive sheets. The first encapsulant encapsulates the die, the conductive sheets, and the conductive balls. The first encapsulant exposes at least a portion of each conductive ball.