公开(公告)号：US11367678B2

公开(公告)日：2022-06-21

申请号：US16953362

申请日：2020-11-20

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Chia-Yu Hung ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L23/24 ,  H01L21/78 ,  H01L23/16 ,  H01L23/367 ,  H01L23/552

Abstract: A package structure including a first circuit board, a second circuit board, an encapsulant, a plurality of conductive terminals, and a package device is provided. The first circuit board has a first top surface and a first bottom surface opposite to each other. The second circuit board has a second top surface and a second bottom surface opposite to each other. The encapsulant encapsulates the first and second circuit boards. The conductive terminals are disposed on the first or second bottom surface and electrically connected to the first or second circuit board. The package device is disposed on the first or second top surface and electrically connected to the first and second circuit boards. The package device includes a first chip, a second chip, a chip encapsulant, a circuit layer, and a plurality of conductive package terminals. A manufacturing method of a package structure is also provided.

公开(公告)号：US20220173051A1

公开(公告)日：2022-06-02

申请号：US17159152

申请日：2021-01-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A package structure, including a conductive element, multiple dies, a dielectric body, a circuit layer and a patterned insulating layer, is provided. The multiple dies are disposed on the conductive element. A portion of the conductive element surrounds the multiple dies. The dielectric body covers the multiple dies. The circuit layer is disposed on the dielectric body. The circuit layer is electrically connected to the multiple dies. The patterned insulating layer covers the circuit layer. A portion of the patterned insulating layer is disposed between the dies that are adjacent. A manufacturing method of a package structure is also provided.

公开(公告)号：US20220165673A1

公开(公告)日：2022-05-26

申请号：US17330416

申请日：2021-05-26

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure including a first die, a second die, a dielectric body, a conductive terminal, a circuit layer and a patterned insulating layer is provided. The second die is disposed on the first die. A second active surface of the second die faces a first active surface of the first die. The dielectric body covers the first die. The conductive terminal is disposed on the dielectric body and opposite to the second die. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first die is electrically connected to the conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. The second die is electrically connected to the first die through the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric body.

公开(公告)号：US11211321B2

公开(公告)日：2021-12-28

申请号：US17099802

申请日：2020-11-17

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L21/683 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L23/24 ,  H01L21/78 ,  H01L23/16 ,  H01L23/367 ,  H01L23/552

Abstract: A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body.

公开(公告)号：US11094654B2

公开(公告)日：2021-08-17

申请号：US16529796

申请日：2019-08-02

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.

公开(公告)号：US11088100B2

公开(公告)日：2021-08-10

申请号：US16513726

申请日：2019-07-17

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.

公开(公告)号：US20210050296A1

公开(公告)日：2021-02-18

申请号：US16568256

申请日：2019-09-12

Applicant: Powertech Technology Inc.

Inventor： Pei-Chun Tsai ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58 ,  H01L21/48 ,  H01L25/00

Abstract: A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US20210050294A1

公开(公告)日：2021-02-18

申请号：US16703809

申请日：2019-12-04

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Pei-Chun Tsai ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/535 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A fan-out chip package assembly with fine pitch silicon through via uses one or more silicon interposers in the bottom package as interconnections between the top package and the substrate. The one or more partially distributed silicon interposers may be disposed in the same layer of the bottom semiconductor die according to the design requirement of the fan-out contact pads of the top package, allowing more design freedom of the top high level chips.

公开(公告)号：US20200343231A1

公开(公告)日：2020-10-29

申请号：US16398246

申请日：2019-04-29

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L25/16 ,  H01L23/053 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: A package structure including a frame structure, a die, an encapsulant, a redistribution structure, and a passive component is provided. The frame structure has a cavity. The die is disposed in the cavity. The encapsulant fills the cavity to encapsulate the die. The redistribution structure is disposed on the encapsulant, the die, and the frame structure. The redistribution structure is electrically coupled to the die. The passive component is disposed on the frame structure and electrically coupled to the redistribution structure through the frame structure. A manufacturing method of a package structure is also provided. The frame structure may provide support, reduce warpage, dissipate heat from the die, act as a shield against electromagnetic interference, and/or provide electrical connection for grounding.

公开(公告)号：US20200273803A1

公开(公告)日：2020-08-27

申请号：US16513726

申请日：2019-07-17

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Nan-Chun Lin ,  Shang-Yu Chang Chien

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.