公开(公告)号：US07911862B2

公开(公告)日：2011-03-22

申请号：US12585428

申请日：2009-09-15

Applicant: Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

Inventor： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC: G11C7/00

CPC classification number: G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

Abstract translation: 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07907693B2

公开(公告)日：2011-03-15

申请号：US11812438

申请日：2007-06-19

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC: H04L7/00

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

公开(公告)号：US07768298B2

公开(公告)日：2010-08-03

申请号：US12219213

申请日：2008-07-17

Applicant: Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

Inventor： Kwang-Il Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/017545

Abstract: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

Abstract translation: 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

公开(公告)号：US20100134175A1

公开(公告)日：2010-06-03

申请号：US12619280

申请日：2009-11-16

Applicant: Cheon-An Lee ,  Seong-Jin Jang ,  Sang-Woong Shin

Inventor： Cheon-An Lee ,  Seong-Jin Jang ,  Sang-Woong Shin

IPC: H01H85/00

CPC classification number: G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antifuse circuit includes a protection circuit. The antifuse circuit receives a program voltage using a non-connection (NC) pin or ball of a semiconductor device. The protection circuit prevents an unintended voltage lower than the program voltage from being applied to the antifuse circuit.

Abstract translation: 反熔断电路包括保护电路。 反熔丝电路使用半导体器件的非连接（NC）引脚或球来接收编程电压。 保护电路防止低于编程电压的非预期电压被施加到反熔丝电路。

公开(公告)号：US20100091600A1

公开(公告)日：2010-04-15

申请号：US12635785

申请日：2009-12-11

Applicant: Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

Inventor： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G06F12/02 ,  G11C7/1078 ,  G11C7/109

Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

Abstract translation: 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US07663413B2

公开(公告)日：2010-02-16

申请号：US11483422

申请日：2006-07-07

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K17/6872 ,  H03K17/161 ,  Y10T307/74

Abstract: A line driver circuit for stabilizing a signal that is output through a transmission line, wherein the line driver circuit receives a first signal having a first swing width corresponding to a difference between a first voltage and a second voltage, creates a second signal having a second swing width less than the first swing width, and outputs the second signal through a transmission line. The line driver circuit includes: a pull-up circuit that pulls up the second signal to a high level; a pull-down circuit that is connected to the pull-up circuit and pulls down the second signal to a low level; and an initializing circuit that is connected to a node of the transmission line, outputs a signal having a voltage of the low level or the high level to the node of the transmission line, and initializes the voltage at the node of the transmission line to the low level or the high level.

Abstract translation: 一种用于稳定通过传输线输出的信号的线路驱动器电路，其中线路驱动电路接收具有与第一电压和第二电压之间的差对应的第一摆幅宽度的第一信号，产生具有第二信号的第二信号 摆动宽度小于第一摆动宽度，并通过传输线输出第二信号。 线路驱动电路包括：将第二信号拉高至高电平的上拉电路; 下拉电路，连接到上拉电路并将第二信号拉低至低电平; 以及连接到传输线节点的初始化电路，将具有低电平或高电平的电压的信号输出到传输线的节点，并将传输线节点处的电压初始化为 低水平或高水平。

公开(公告)号：US07609584B2

公开(公告)日：2009-10-27

申请号：US11594807

申请日：2006-11-09

Applicant: Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

Inventor： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

Abstract translation: 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07546497B2

公开(公告)日：2009-06-09

申请号：US11419155

申请日：2006-05-18

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G11C29/34 ,  G11C29/50

CPC classification number: G11C29/14 ,  G11C29/12015 ,  G11C29/32

Abstract: A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a first mode and configured to generate the parallel data at the parallel data rate in response to a second serial data at second serial data rate in a second mode, wherein the second serial data rate is less than the first serial data rate, and a data write circuit configured to provide the parallel data to a memory cell array.

Abstract translation: 半导体存储器件包括串行到并行转换器，其被配置为响应于处于第一模式的第一串行数据速率的第一串行数据以并行数据速率产生并行数据，并且被配置为响应于并行数据速率以并行数据速率生成并行数据 以第二模式的第二串行数据速率的第二串行数据，其中所述第二串行数据速率小于所述第一串行数据速率，以及数据写入电路，被配置为将并行数据提供给存储器单元阵列。

公开(公告)号：US07541947B2

公开(公告)日：2009-06-02

申请号：US11802886

申请日：2007-05-25

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

IPC: H03M7/00

CPC classification number: H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

公开(公告)号：US07525345B2

公开(公告)日：2009-04-28

申请号：US11503802

申请日：2006-08-14

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/01707 ,  H03K19/0013

Abstract: A swing limiter comprises a logic circuit including a first pull-up transistor and a first pull-down transistor connected between first and second nodes and which generate an output signal; a second pull-up transistor connected between a first power voltage and the first node; a second pull-down transistor connected between the second node and a second power voltage; a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage; and a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage.

Abstract translation: 摆动限制器包括逻辑电路，该逻辑电路包括连接在第一和第二节点之间并产生输出信号的第一上拉晶体管和第一下拉晶体管; 连接在第一电源电压和第一节点之间的第二上拉晶体管; 连接在第二节点和第二电源电压之间的第二下拉晶体管; 连接在高于第一电源电压的高电压和低于高电压的第一参考电压之间的第一控制电压发生器; 以及第二控制电压发生器，其连接在低于所述第二电力电压的低电压和高于所述低电压的第二参考电压。