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公开(公告)号：US08847389B1
公开(公告)日：2014-09-30
申请号：US13889053
申请日：2013-05-07
Inventor： Jung-Hua Chang , Cheng-Lin Huang , Jing-Cheng Lin
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49816 , H01L23/481 , H01L23/49827 , H01L23/49894 , H01L2224/13
Abstract: A method and apparatus for a conductive bump structure is provided. The conductive bump structure may include a conductive layer and a conductive bump formed over a through via (“TV”). The TV may be formed through a substrate and a passivation layer. The TV may have a top surface extending above a top surface of the passivation layer. The conductive layer may be formed directly over the TV using one or more electroless plating processes. The conductive layer may have sides that may taper from a top surface of the conductive layer to the top surface of the passivation layer. The conductive layer may include a plurality of layers, wherein each layer may be formed using one or more electroless plating processes. The conductive bump may be formed on the conductive layer and may be reflowed to couple the conductive bump to the conductive layer.
Abstract translation: 提供了一种用于导电凸块结构的方法和装置。 导电凸块结构可以包括在通孔（“TV”）上形成的导电层和导电凸块。 TV可以通过衬底和钝化层形成。 TV可以具有在钝化层的顶表面上方延伸的顶表面。 可以使用一个或多个无电镀方法直接在电视机上形成导电层。 导电层可以具有可以从导电层的顶表面到钝化层的顶表面逐渐变细的侧面。 导电层可以包括多个层，其中每个层可以使用一个或多个无电镀方法形成。 导电凸块可以形成在导电层上，并且可以被回流以将导电凸块耦合到导电层。
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公开(公告)号：US20140287581A1
公开(公告)日：2014-09-25
申请号：US14299886
申请日：2014-06-09
Inventor： Yung-Chi Lin , Sylvia Lo , Jing-Cheng Lin , Yen-Hung Chen , Wen-Chih Chiou
IPC: H01L21/768
CPC classification number: H01L21/76898 , H01L21/7685 , H01L21/76877 , H01L23/481 , H01L24/03 , H01L24/05 , H01L2224/0346 , H01L2224/03616 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05025 , H01L2224/05026 , H01L2224/05099 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05541 , H01L2224/05571 , H01L2224/05599 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2924/00014 , H01L2924/00012 , H01L2924/207 , H01L2224/05552
Abstract: A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.
Abstract translation: 公开了一种用于向TSV提供沉积在TSV的顶表面下方的阻挡层的系统和方法，顶表面具有减小的地形变化。 将底部TSV焊盘沉积到通孔中，然后抛光，使得顶表面在衬底顶表面下方。 然后在通孔中沉积阻挡层，并且沉积在阻挡层上的顶部TSV焊盘。 顶部的TSV屏障垫被抛光，以使顶部TSV焊盘的顶部表面与衬底的高度一致。 阻挡垫可以小于约1微米厚，并且顶部TSV垫可以小于约6微米厚。 阻挡垫可以是来自顶部和底部TSV垫的不同金属，并且可以选自包括钛，钽，钴，镍等的组。
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公开(公告)号：US20140264843A1
公开(公告)日：2014-09-18
申请号：US13901279
申请日：2013-05-23
Inventor： Jing-Cheng Lin , Cheng-Lin Huang
IPC: H01L23/00
CPC classification number: H01L24/81 , H01L21/4853 , H01L21/486 , H01L23/293 , H01L23/3192 , H01L23/49811 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/1134 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/13005 , H01L2224/13017 , H01L2224/13018 , H01L2224/13026 , H01L2224/13084 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16058 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/16503 , H01L2224/16507 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/8181 , H01L2224/81815 , H01L2225/06513 , H01L2924/15311 , H01L2924/3656 , H01L2924/00014 , H01L2924/206 , H01L2924/00012 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
Abstract: An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer.
Abstract translation: 一个实施例是集成电路结构，其包括具有凸块结构的第一管芯和具有衬垫结构的第二管芯。 通过结合凸起结构和垫结构，将第一模具附接到第二模具。 凸块结构包括金属支柱，金属支柱上的金属盖层，金属盖层上的金属插入层和金属插入层上的焊料层。 垫结构包括镍（Ni）层，钯（Pd）层或金（Au）层中的至少一种。
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84.发明申请Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices 有权封装半导体器件，封装半导体器件和PoP器件的方法公开(公告)号：US20140264839A1
公开(公告)日：2014-09-18
申请号：US13890162
申请日：2013-05-08
Inventor： Po-Hao Tsai , Jui-Pin Hung , Jing-Cheng Lin
IPC: H01L23/498 , H01L21/768
CPC classification number: H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L21/78 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/03 , H01L24/19 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/02317 , H01L2224/033 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/19 , H01L2224/32145 , H01L2224/32225 , H01L2224/73265 , H01L2224/73267 , H01L2224/8392 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1047 , H01L2225/1058 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2224/48227 , H01L2924/00012 , H01L2224/82 , H01L2924/00 , H01L2224/83 , H01L2224/83005
Abstract: Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads.
Abstract translation: 公开了封装半导体器件，封装半导体器件的方法和封装封装（PoP）器件。 在一些实施例中，封装半导体器件的方法包括在载体上形成贯穿封装通孔（TPV），以及将半导体器件耦合到载体。 半导体器件包括设置在其表面上的接触焊盘和设置在接触焊盘上的绝缘材料。 在TPV和半导体器件之间的载体上形成模制材料。 使用在接触焊盘上的激光钻孔工艺在绝缘材料中形成开口，并且在绝缘材料和绝缘材料中的开口上形成再分布层（RDL）。 RDL的一部分耦合到每个接触焊盘的顶表面。
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公开(公告)号：US20140264828A1
公开(公告)日：2014-09-18
申请号：US13795081
申请日：2013-03-12
Inventor： Jung-Hua Chang , Cheng-Lin Huang , Nai-Wei Liu , Jui-Pin Hung , Jing-Cheng Lin
IPC: H01L23/00
CPC classification number: H01L24/17 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L2224/0312 , H01L2224/03462 , H01L2224/03464 , H01L2224/0384 , H01L2224/0391 , H01L2224/0401 , H01L2224/05022 , H01L2224/05111 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05184 , H01L2224/05556 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/1112 , H01L2224/13017 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/15787 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.
Abstract translation: 提供一种用于导电柱结构的方法和装置。 可以提供一种器件，其可以包括衬底，在衬底上形成的第一钝化层，延伸穿过第一钝化层并进入衬底的导电互连，在第一钝化层上形成的导电焊盘，以及第二钝化层 形成在互连焊盘和第二钝化层上。 互连焊盘的一部分可以从第二钝化层露出。 导电柱可以使用一个或多个无电镀工艺直接形成在互连焊盘上。 导电柱可以具有第一宽度和第二宽度，第一高度对应于第一宽度和第二宽度之间的距离。
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Patent Agency Ranking
公开(公告)号：US08796849B2
公开(公告)日：2014-08-05
申请号：US13656968
申请日：2012-10-22
Inventor： Jing-Cheng Lin
CPC classification number: H01L24/17 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/023 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05082 , H01L2224/05558 , H01L2224/05572 , H01L2224/11 , H01L2224/1145 , H01L2224/1146 , H01L2224/11462 , H01L2224/116 , H01L2224/13 , H01L2224/13022 , H01L2224/13023 , H01L2224/13024 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/13655 , H01L2224/1601 , H01L2224/16058 , H01L2224/16145 , H01L2224/16148 , H01L2224/16238 , H01L2224/16503 , H01L2224/175 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2924/0105 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/00012 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
Abstract: A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.
Abstract translation: 一种结构包括具有第一金属凸块的第一半导体芯片和具有第二金属凸块的第二半导体芯片。 所述结构还包括电连接所述第一半导体芯片和所述第二半导体芯片的焊接结构，其中所述焊点结构包括在所述第一金属凸块和所述第二金属凸块之间的金属间化合物区域，其中所述金属间化合物区域具有第一 高度尺寸和沿着第一金属凸块和第二金属凸块的外壁形成的周围部分，其中周围部分具有第二高度尺寸，并且其中第二高度尺寸大于第一高度尺寸。
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公开(公告)号：US08796829B2
公开(公告)日：2014-08-05
申请号：US13624471
申请日：2012-09-21
Inventor： Jing-Cheng Lin
IPC: H01L21/00
CPC classification number: H01L23/367 , H01L21/486 , H01L23/10 , H01L23/3677 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L23/585 , H01L24/16 , H01L24/29 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/05552 , H01L2224/05568 , H01L2224/0557 , H01L2224/05572 , H01L2224/0618 , H01L2224/06181 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/14181 , H01L2224/16146 , H01L2224/16238 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/16251 , H01L2924/181 , H01L2924/014 , H01L2924/00
Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.
Abstract translation: 封装包括芯片，其包括半导体衬底，穿过半导体衬底的多个通孔，与多个通孔重叠并连接的密封环，以及在半导体衬底下方连接的多个电连接器 到密封圈。 插入器是底层的，并粘贴在模具上。 插入器包括衬底和衬底上的多个金属线。 多个金属线电耦合到多个电连接器。 多个金属线中的每一条具有与第一模具重叠的第一部分和与模具不对准的第二部分。 导热块环绕模具，并且安装在插入件的多个金属线上。
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公开(公告)号：US20140210080A1
公开(公告)日：2014-07-31
申请号：US13753204
申请日：2013-01-29
Inventor： Chin-Chuan Chang , Jing-Cheng Lin , Nai-Wei Liu , Wan-Ting Shih
IPC: H01L23/498 , H01L21/50
CPC classification number: H01L23/49816 , H01L21/50 , H01L21/568 , H01L23/49822 , H01L23/538 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/73 , H01L24/96 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L25/10 , H01L25/117 , H01L25/162 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/80001 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2924/00012 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/83 , H01L2224/82
Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.
Abstract translation: 形成PoP器件的方法包括将粘合剂层放置在载体衬底上，将多个芯片封装耦合到载体衬底上的粘合剂层，将结合层放置在芯片封装上，以及将多个芯片耦合到键合 层上的芯片封装。 该方法还包括注射模塑料以将芯片封装和芯片封装在载体衬底上，研磨模塑料以暴露芯片的多个连接元件和芯片封装的多个第二连接元件，从而形成再分配 层（RDL）和暴露的连接元件和第二连接元件，在RDL上形成球栅阵列（BGA），并且使载体基板去粘合。
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89.发明申请Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages 有权半导体器件，其制造方法和半导体器件封装公开(公告)号：US20140210074A1
公开(公告)日：2014-07-31
申请号：US13753312
申请日：2013-01-29
Inventor： I-Ting Chen , Ying-Ching Shih , Po-Hao Tsai , Szu Wei Lu , Jing-Cheng Lin
IPC: H01L23/498 , H01L21/768
CPC classification number: H01L23/49811 , H01L21/76885 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/50 , H01L2224/0345 , H01L2224/0348 , H01L2224/03912 , H01L2224/0401 , H01L2224/0508 , H01L2224/05166 , H01L2224/05647 , H01L2224/06102 , H01L2224/10126 , H01L2224/1146 , H01L2224/11474 , H01L2224/1148 , H01L2224/1161 , H01L2224/11618 , H01L2224/11622 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13019 , H01L2224/13022 , H01L2224/13082 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/13166 , H01L2224/13187 , H01L2224/1319 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/1701 , H01L2224/17051 , H01L2224/17517 , H01L2224/81141 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/014 , H01L2924/05042 , H01L2924/00012 , H01L2924/00
Abstract: Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.
Abstract translation: 公开了半导体器件，其制造方法和半导体器件封装。 在一个实施例中，半导体器件包括在衬底的表面上具有开口的绝缘材料层。 一个或多个插入凸块设置在绝缘材料层上。 半导体器件包括具有未设置在绝缘材料层上的部分的信号凸块。
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公开(公告)号：US08785299B2
公开(公告)日：2014-07-22
申请号：US13691536
申请日：2012-11-30
Inventor： Yi-Chao Mao , Chin-Chuan Chang , Jui-Pin Hung , Jing-Cheng Lin
IPC: H01L21/00
CPC classification number: H01L23/49811 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L23/3128 , H01L23/3135 , H01L23/3192 , H01L23/48 , H01L24/19 , H01L24/97 , H01L2221/68327 , H01L2221/68372 , H01L2224/12105 , H01L2224/13 , H01L2924/12042 , H01L2924/15787 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.
Abstract translation: 一个实施方案是包括半导体管芯，半导体管芯的第一侧上的粘合剂层和围绕半导体管芯和粘合剂层的模制化合物的器件，其中模塑料与粘合剂层处于相同的水平。 该器件还包括电耦合到半导体管芯的第二侧的第一钝化后互连（PPI）和电耦合到第一PPI的第一连接器，其中第一连接器在模制化合物上方并对齐。
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