公开(公告)号：US20240413239A1

公开(公告)日：2024-12-12

申请号：US18525638

申请日：2023-11-30

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Daniel Pham ,  Sujatha Sampath ,  Ali Saadat ,  Orlando Lazaro ,  Vijay K. Reddy ,  Steven Kummerl

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: Disclosed examples include microelectronic devices, e.g. Integrated circuits. One example includes a microelectronic device including a nanosheet lateral drain extended metal oxide semiconductor (LDMOS) transistor with source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type. A superlattice of alternating layers of nanosheets of a channel region and layers of gate conductor are separated by a gate dielectric, the superlattice extending between the source region and the drain region. A drain drift region of the first conductivity type extends under the drain region and a body region of the second type extends around the source region.

公开(公告)号：US20240282854A1

公开(公告)日：2024-08-22

申请号：US18654431

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Andres Arturo Blanco ,  Orlando Lazaro

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7826 ,  H01L29/66681

Abstract: IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.

公开(公告)号：US12015057B2

公开(公告)日：2024-06-18

申请号：US17156612

申请日：2021-01-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Alexei Sadovnikov ,  Henry Litzmann Edwards ,  Jarvis Benjamin Jacobs

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/26 ,  H01L29/66

CPC classification number: H01L29/26 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

公开(公告)号：US11984475B2

公开(公告)日：2024-05-14

申请号：US17536391

申请日：2021-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Joseph Maurice Khayat ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L29/0626 ,  H01L29/66113 ,  H01L29/861

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

公开(公告)号：US11721779B2

公开(公告)日：2023-08-08

申请号：US17246068

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rahmi Hezar ,  Henry Litzmann Edwards

IPC: H01L31/107 ,  H01L31/109 ,  H01L31/02

CPC classification number: H01L31/107 ,  H01L31/02027 ,  H01L31/109

Abstract: An integrated circuit includes a photodetector that has an epitaxial layer with a first conductivity type located over a substrate. A buried layer of the first conductivity type is located within the epitaxial layer and has a higher carrier concentration than the epitaxial layer. A semiconductor layer located over the buried layer has an opposite second conductivity type and includes a first sublayer over the buried semiconductor layer and a second sublayer between the first sublayer and the buried layer. The first sublayer has a larger lateral dimension than the second sublayer, and has a lower carrier concentration than the second sublayer.

公开(公告)号：US20230170384A1

公开(公告)日：2023-06-01

申请号：US17536391

申请日：2021-11-29

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Joseph Maurice Khayat ,  Archana Venugopal

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/0626 ,  H01L29/861 ,  H01L29/66113

Abstract: An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

公开(公告)号：US11594630B2

公开(公告)日：2023-02-28

申请号：US17329334

申请日：2021-05-25

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L21/22 ,  H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/225

Abstract: An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.

公开(公告)号：US20220384636A1

公开(公告)日：2022-12-01

申请号：US17329334

申请日：2021-05-25

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/225 ,  H01L29/66 ,  H01L27/088

Abstract: An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.

公开(公告)号：US20220271159A1

公开(公告)日：2022-08-25

申请号：US17487209

申请日：2021-09-28

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Henry Litzmann Edwards ,  Curry Bachman Taylor

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure in a silicon recess on the silicon portion of the hybrid device. The silicon recess contains a silicon recess nitride sidewall. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon.

公开(公告)号：US11411070B2

公开(公告)日：2022-08-09

申请号：US16897373

申请日：2020-06-10

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/762 ,  H01L29/92 ,  H01L21/32 ,  H01L27/08 ,  H01L29/94

Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.