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    Manufacturing method of semiconductor memory device
    81.
    发明授权
    Manufacturing method of semiconductor memory device 有权

    公开(公告)号：US11069689B2

    公开(公告)日：2021-07-20

    申请号：US16789435

    申请日：2020-02-13

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng ,  Yu-Cheng Tung

    IPC: H01L27/108 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

    Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A contact hole is formed on a memory cell region of a semiconductor substrate and exposes a part of the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on a memory cell region of the semiconductor substrate. A second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. A contact structure is formed in the contact hole, and the contact structure is located between the bit line metal structure and the semiconductor substrate.

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    83.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210043684A1

    公开(公告)日：2021-02-11

    申请号：US17082034

    申请日：2020-10-28

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Tzu-Tsen Liu ,  Tsung-Ying Tsai ,  Chien-Ting Ho

    IPC: H01L27/24 ,  H01L27/108 ,  H01L21/02 ,  H01L21/764

    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

    Manufacturing method of semiconductor memory device
    84.
    发明授权
    Manufacturing method of semiconductor memory device 有权

    公开(公告)号：US10600790B2

    公开(公告)日：2020-03-24

    申请号：US15987919

    申请日：2018-05-24

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng ,  Yu-Cheng Tung

    IPC: H01L27/108 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

    Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate is provided. A memory cell region and a peripheral region are defined on the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on the memory cell region, and a second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. In the present invention, the replacement metal gate process is used to form the bit line metal structure for reducing the electrical resistance of the bit lines.

    Insulating structure and method of forming the same
    85.
    发明授权
    Insulating structure and method of forming the same 有权

    公开(公告)号：US10475795B2

    公开(公告)日：2019-11-12

    申请号：US15729682

    申请日：2017-10-11

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng

    IPC: H01L27/108 ,  H01L21/311 ,  H01L21/033

    Abstract: A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

    Semiconductor memory device and manufacturing method thereof
    87.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权

    公开(公告)号：US10276577B2

    公开(公告)日：2019-04-30

    申请号：US15884399

    申请日：2018-01-31

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

    IPC: H01L29/76 ,  H01L29/94 ,  H01L27/108

    Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

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