公开(公告)号：US20140242500A1

公开(公告)日：2014-08-28

申请号：US14273419

申请日：2014-05-08

Applicant: SEMATECH, INC. ,  ASAHI GLASS CO., LTD.

Inventor： Vibhu Jindal ,  Junichi Kageyama

IPC: G03F1/22 ,  B08B7/04 ,  C23C14/56

CPC classification number: G03F1/22 ,  B08B7/04 ,  B82Y10/00 ,  B82Y40/00 ,  C23C14/34 ,  C23C14/564 ,  G03F1/60

Abstract: A process for cleaning and restoring deposition shield surfaces which results in a cleaned shield having a surface roughness of between about 200 microinches and about 500 microinches and a particle surface density of less than about 0.1 particles/mm2 of particles between about 1 micron and about 5 microns in size and no particles less than about 1 micron in size and method for use thereof is disclosed.

Abstract translation: 一种用于清洁和恢复沉积屏蔽表面的方法，其导致具有约200微英寸至约500微英寸之间的表面粗糙度和小于约0.1微米/ mm 2的颗粒的颗粒表面密度在约1微米至约5微米之间的清洁屏蔽 公开了尺寸微米和尺寸小于约1微米的颗粒及其使用方法。

公开(公告)号：US20140206112A1

公开(公告)日：2014-07-24

申请号：US14157804

申请日：2014-01-17

Applicant: Sematech, Inc. ,  The Research Foundation for the State University of New York

Inventor： MELVIN WARREN MONTGOMERY ,  Cecilia Annette Montgomery ,  Benjamin D. Bunday

IPC: H01L21/66 ,  H01L21/033

CPC classification number: H01L22/12 ,  G01B15/00 ,  G01B2210/56 ,  G01N23/2251 ,  G01N2223/6116 ,  G03F7/075 ,  G03F7/0752 ,  G03F7/0757 ,  G03F7/091 ,  G03F7/2004 ,  H01L21/0276

Abstract: Methods and compositions are provided for reducing or eliminating charge buildup during scanning electron microscopy (SEM) metrology of a critical dimension (CD) in a structure produced by lithography. An under layer is utilized that comprises silicon in the construction of the structure. When the lithography structure comprising the silicon-comprising under layer is scanned for CDs using SEM, the under layer reduces or eliminates charge buildup during SEM metrological observations.

Abstract translation: 提供的方法和组合物用于在通过光刻产生的结构中的临界尺寸（CD）的扫描电子显微镜（SEM）计量学中减少或消除电荷累积。 在结构的结构中使用包含硅的底层。 当使用SEM扫描包含含硅底层的光刻结构时，下层在SEM测量观察期间减少或消除电荷累积。

公开(公告)号：US20140054549A1

公开(公告)日：2014-02-27

申请号：US13592805

申请日：2012-08-23

Applicant: Wei-Yip LOH ,  Wei-E WANG

Inventor： Wei-Yip LOH ,  Wei-E WANG

IPC: H01L29/775 ,  H01L21/20

CPC classification number: H01L29/66356 ,  H01L29/205 ,  H01L29/7391

Abstract: A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer.

Abstract translation: 提供半导体器件和隧道场效应晶体管及其制造方法。 该器件包括第一和第二半导体区域，中间区域和外延层。 中间区域分离第一和第二半导体区域，并且外延层至少部分地在第一和第二区域之间在中间区域的上方或旁边延伸。 提供栅电极用于选通电路结构。 外延层被设置为位于栅电极和第一半导体区域，第二半导体区域或中间区域中的至少一个之间。 外延层包括厚度小于或等于15纳米的外延生长的半导体材料超薄体层。 在半导体器件是隧道场效应晶体管的情况下，中间区域可以是大的带隙半导体区域，其带隙大于外延层的带隙。

公开(公告)号：US20130320427A1

公开(公告)日：2013-12-05

申请号：US13487627

申请日：2012-06-04

Applicant: Wei-Yip LOH ,  Richard HILL ,  Prashant MAJHI

Inventor： Wei-Yip LOH ,  Richard HILL ,  Prashant MAJHI

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L29/7391 ,  H01L29/66356

Abstract: A tunnel field-effect transistor is provided, which includes a fin-shaped, source-drain circuit structure with a source region and a drain region. The circuit structure is angled in cross-sectional elevation, and includes a first portion and a second portion. The first portion extends away from the second portion, and the source region is disposed in the first or second portion, and the drain region is disposed in the other of the first or second portion. The transistor further includes a gate electrode for gating the circuit structure and a self-aligned tunneling region. The tunneling region is self-aligned to at least a portion of the circuit structure and extends between the gate electrode and the first or second portion of the fin-shaped circuit structure, and the self-aligned tunneling region is at least partially disposed in parallel, spaced opposing relation to a control surface of the gate electrode.

Abstract translation: 提供一种隧道场效应晶体管，其包括具有源极区和漏极区的鳍状源极 - 漏极电路结构。 电路结构在横截面的高度上成角度，并且包括第一部分和第二部分。 第一部分远离第二部分延伸，并且源极区域设置在第一或第二部分中，并且漏极区域设置在第一部分或第二部分中的另一个部分中。 晶体管还包括用于选通电路结构的栅极电极和自对准的隧穿区域。 隧道区域与电路结构的至少一部分自对准，并且在栅电极和鳍状电路结构的第一或第二部分之间延伸，并且自对准隧道区域至少部分地平行设置 与栅电极的控制表面间隔相对的关系。

公开(公告)号：US20130320359A1

公开(公告)日：2013-12-05

申请号：US13487694

申请日：2012-06-04

Applicant: Klaus HUMMLER

Inventor： Klaus HUMMLER

IPC: H01L23/48 ,  H01L31/12 ,  H01L31/02 ,  H01L27/144

CPC classification number: G02B6/43 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1443 ,  H01L2224/13099 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06534 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A heterogeneous stack structure is provided which includes one or more optical signal-based chips and multiple electrical signal-based chips. The optical chip(s) and the electrical chip(s) are different layers of the stack structure, and the optical chip(s) includes optical signal paths extending at least partially laterally within the optical chip(s). Electrical signal paths are provided extending between and coupling the optical chip(s) and the electrical chips. The electrical signal paths include one or more through substrate vias (TSVs) through one or more electrical chips of the multiple electrical chips in the stack structure. In one embodiment, the optical chip(s) is configured laterally to locally distribute, via one or more paths of the electrical signal paths, a timing reference signal for one or more electrical chips in the stack. Conversion between optical and electrical signals within the stack structure occurs within the optical chip(s).

Abstract translation: 提供了包括一个或多个基于光信号的芯片和多个基于电信号的芯片的异构堆栈结构。 光学芯片和电气芯片是堆叠结构的不同层，并且光学芯片包括在光学芯片内部至少部分地横向延伸的光学信号路径。 提供的电信号通路在光学芯片和电气芯片之间延伸并耦合。 电信号路径包括通过堆叠结构中的多个电子芯片的一个或多个电气芯片的一个或多个通过衬底通孔（TSV）。 在一个实施例中，光学芯片被侧向配置以经由电信号路径的一个或多个路径局部地分配用于堆叠中的一个或多个电气芯片的定时参考信号。 堆叠结构内的光和电信号之间的转换发生在光学芯片内。

公开(公告)号：US20130122708A1

公开(公告)日：2013-05-16

申请号：US13734593

申请日：2013-01-04

Applicant: SEMATECH, INC.

Inventor： Matt Malloy

IPC: H01L21/306 ,  H01L21/30

CPC classification number: H01L21/306 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/30

Abstract: Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.

Abstract translation: 公开了在光刻工艺中由半导体芯片的部分裸片的方便处理的方法，系统和装置。 实施例利用不与部分模具进行物理接触的压印式模板进行曝光。 在一个实施例中，公开了一种具有至少一个完整管芯和至少一个部分管芯的半导体工艺。 部分地通过使用蚀刻工艺来制造半导体芯片，该蚀刻工艺利用当压印模板与被分配到至少一个完整裸片上的抗蚀剂接触时构造成暴露于至少一个全裸片的印模模板 。 此外，半导体芯片的至少一个部分裸片被配置为暴露于压印模板，而不将模板接触抗蚀剂分配到至少一个部分裸片上。

公开(公告)号：US08432020B2

公开(公告)日：2013-04-30

申请号：US12794251

申请日：2010-06-04

Applicant: Chanro Park ,  Sangduk Park ,  Paul D. Kirsch ,  David Gilmer ,  Chang Yong Kang ,  Joel Barnett

Inventor： Chanro Park ,  Sangduk Park ,  Paul D. Kirsch ,  David Gilmer ,  Chang Yong Kang ,  Joel Barnett

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L28/65

Abstract: Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Abstract translation: 公开了电容器，系统和方法。 在一个实施例中，电容器包括第一电极。 电容器还可以包括具有与第一电极相邻的正VCC的第一绝缘体层。 电容器还可以包括具有邻近第一绝缘体层的负VCC的第二绝缘体层。 电容器还可以包括具有与第二绝缘体层相邻的正VCC的第三绝缘体层。 电容器还可以包括与第三绝缘体层相邻的第二电极。

公开(公告)号：US20130093029A1

公开(公告)日：2013-04-18

申请号：US13271522

申请日：2011-10-12

Applicant: Jung Hwan YUM ,  Gennadi Bersuker ,  K. Sanjay Banerjee

Inventor： Jung Hwan YUM ,  Gennadi Bersuker ,  K. Sanjay Banerjee

IPC: H01L21/316 ,  H01L29/78 ,  H01L29/12

CPC classification number: H01L21/316 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28211 ,  H01L29/517

Abstract: A process for creating a beryllium oxide film on the surface of a semiconductor material is disclosed. The process is useful for making gate dielectric layers for metal-oxide-semiconductor (MOS) devices, particularly III-V semiconductor devices.

Abstract translation: 公开了一种在半导体材料的表面上形成氧化铍膜的方法。 该方法可用于制备用于金属氧化物半导体（MOS）器件的栅极电介质层，特别是III-V半导体器件。

公开(公告)号：US08399868B2

公开(公告)日：2013-03-19

申请号：US13027804

申请日：2011-02-15

Applicant: Vibhu Jindal ,  Andrea Wüest

Inventor： Vibhu Jindal ,  Andrea Wüest

IPC: C23F1/00 ,  H01L21/306

CPC classification number: G21K1/062 ,  B82Y10/00 ,  G03F7/70925

Abstract: Devices, tools, and methods for mitigating contamination of an optics surface used in extreme ultraviolet (EUV) applications disclosed. The method may include providing an optically reflective surface configured to reflect EUV radiation. The method may further include exposing the optically reflective surface to EUV radiation thereby generating electrons. The method may also include applying an electromagnetic field to the optically reflective surface, the electromagnetic field configured to reduce reactions initiated by the electrons on the optically reflective surface. The applied electromagnetic field may be constant or varied and also may have different biases.

Abstract translation: 公开了用于减轻在极紫外（EUV）应用中使用的光学表面污染的装置，工具和方法。 该方法可以包括提供被配置为反射EUV辐射的光学反射表面。 该方法还可以包括将光反射表面暴露于EUV辐射，从而产生电子。 该方法还可以包括将电磁场施加到光学反射表面，电磁场被配置为减少由光学反射表面上的电子引发的反应。 施加的电磁场可以是恒定的或变化的，并且也可以具有不同的偏差。

公开(公告)号：US08206510B2

公开(公告)日：2012-06-26

申请号：US13027923

申请日：2011-02-15

Applicant: Abbas Rastegar ,  Yoshiaki Ikuta

Inventor： Abbas Rastegar ,  Yoshiaki Ikuta

IPC: B08B3/10

CPC classification number: B08B3/10 ,  B05D3/062 ,  B08B7/0057 ,  H01L21/67051 ,  H01L21/67115

Abstract: The present invention provides an apparatus and a method for an ultraviolet cleaning tool. The cleaning tool includes ultraviolet source spaced apart from a surface having contaminant particles. The ultraviolet source can create ozone between the surface and the ultraviolet source which breaks the chemical bonds between particles and the surface. The apparatus includes a gas feed which introduces a gas to aid the chemical bond. Additionally, the gas feed can introduce a gas to remove the particles from the surface.

Abstract translation: 本发明提供一种紫外线清洁工具的装置和方法。 清洁工具包括与具有污染物颗粒的表面间隔开的紫外线源。 紫外线源可以在表面和紫外线源之间产生臭氧，从而破坏了颗粒与表面之间的化学键。 该装置包括引入气体以辅助化学键的气体进料。 此外，气体进料可以引入气体以从表面除去颗粒。