公开(公告)号：US12014991B2

公开(公告)日：2024-06-18

申请号：US17951474

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Keunwook Shin ,  Kibum Kim ,  Hyunmi Kim ,  Hyeonjin Shin ,  Sanghun Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5386 ,  H01L23/53204 ,  H01L23/5329 ,  H01L24/19 ,  H01L29/1606

Abstract: An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

公开(公告)号：US20240112969A1

公开(公告)日：2024-04-04

申请号：US18360813

申请日：2023-07-28

Applicant: Industrial Technology Research Institute

Inventor： Yu-Ming Peng ,  Hsiao-Fen Wei ,  Chih-Chia Chang

IPC: H01L23/14 ,  H01L23/13 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/145 ,  H01L23/13 ,  H01L23/528 ,  H01L23/53204

Abstract: An in-mold electronic (IME) device includes a curved substrate, a first conductive layer, a dielectric layer, a gap compensation layer, and a second conductive layer. The curved substrate has a first surface. The first conductive layer is disposed on the first surface. The dielectric layer is disposed on the first conductive layer and has a first thickness. The gap compensation layer is disposed on the first surface and connected to the dielectric layer. The gap compensation layer has a second thickness. The second conductive layer is disposed on the gap compensation layer and electrically connected to the gap compensation layer. A curvature radius of the curved substrate is c, a ratio of the second thickness to the first thickness is r, and c and r satisfy a relationship: r=1.5−0.02c±15%.

公开(公告)号：US20240047351A1

公开(公告)日：2024-02-08

申请号：US17882441

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Walter L. Moden

IPC: H01L23/528 ,  H01L21/56 ,  H01L21/308 ,  H01L23/532 ,  H01L23/495 ,  H01L27/105

CPC classification number: H01L23/528 ,  H01L21/563 ,  H01L21/308 ,  H01L23/53204 ,  H01L23/49503 ,  H01L27/105

Abstract: Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative semiconductor device comprises a substrate including a plurality of conductive contacts and a mask material having a surface. The mask material includes (a) a first recess formed in the surface having a first depth and (b) a second recess formed in the surface having a second depth greater than the first depth. An exposed portion of each of the conductive contacts is exposed from the mask material in the second recess. The semiconductor device further comprises a semiconductor die including a lower surface having bond pads, and the lower surface is positioned in the first recess. The semiconductor device further comprises a plurality of conductive features electrically coupling individual ones of the bond pads to corresponding ones of the exposed portions of the conductive contacts.

公开(公告)号：US20230343709A1

公开(公告)日：2023-10-26

申请号：US18342145

申请日：2023-06-27

Applicant: Samsung Electronics Co., Ltd. ,  AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION

Inventor： Youngjae KANG ,  SangWoon LEE ,  Joungeun YOO ,  Duseop YOON

IPC: H01L23/532 ,  H01L21/285 ,  H01L23/528 ,  H01L29/45

CPC classification number: H01L23/53204 ,  H01L21/2855 ,  H01L23/5283 ,  H01L29/45

Abstract: A semiconductor interconnect and an electrode for semiconductor devices may include a thin film including a multielement compound represented by Formula 1 and having a thickness equal to or less than about 50 nm, a grain size (A) to thickness (B) ratio (A/B) equal to or greater than about 1.2, and a resistivity equal to or less than about 200 µΩ·cm:








M

n+1




AX

n





­­­Formula 1







In Formula 1, M, A, X, and n are as described in the specification.

公开(公告)号：US20230326789A1

公开(公告)日：2023-10-12

申请号：US17715215

申请日：2022-04-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HSIH-YANG CHIU

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53204 ,  H01L23/5283

Abstract: The present disclosure provides a semiconductor device having an air cavity. The semiconductor device includes a substrate, a first patterned conductive layer, a first dielectric layer, and a second patterned conductive layer. The first patterned conductive layer is on the substrate. The first dielectric layer is on the first patterned conductive layer. The second patterned conductive layer is on the first dielectric layer. The semiconductor device has an air cavity between the first patterned conductive layer and the second patterned conductive layer.

公开(公告)号：US20230260911A1

公开(公告)日：2023-08-17

申请号：US18306989

申请日：2023-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Fu Tsai ,  Hou-Ju Huang ,  Shih-Ting Lin ,  Szu-Wei Lu ,  Hung-Wei Tsai

IPC: H01L23/532 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/53204 ,  H01L23/29 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/5383

Abstract: A semiconductor device includes a semiconductor die and a conductive structure disposed side-by-side and spaced apart from each other through an insulating encapsulant. The conductive structure includes a first conductor laterally covered by the insulating encapsulant, and a second conductor disposed over and separating from the first conductor. The second conductor includes a first portion laterally covered by the insulating encapsulant and a second portion protruded from the insulating encapsulant, where a ratio of a first standoff height of the first portion and a second standoff height of the second portion ranges from about 0.4 to about 1.5.

公开(公告)号：US20230178487A1

公开(公告)日：2023-06-08

申请号：US17893770

申请日：2022-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungha HWANG ,  Dongchan LIM ,  Seulgi BAE

IPC: H01L23/532

CPC classification number: H01L23/53204 ,  H01L23/5329

Abstract: A semiconductor device including an insulating structure, and a conductive structure in the insulating structure may be provided. The conductive structure includes a barrier layer, an anti-migration layer on the barrier layer, a liner on the anti-migration layer, a conductive layer on the liner, and a capping layer covering a top surface of the barrier layer and a top surface of the anti-migration layer. The capping layer and the liner include Co. The anti-migration layer includes Mn.

公开(公告)号：US11670697B2

公开(公告)日：2023-06-06

申请号：US17353606

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Chih-Yang Yeh ,  Shu-Hui Wang ,  Jeng-Ya David Yeh

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/7684 ,  H01L21/76846 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53204 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/165 ,  H01L29/517 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.

公开(公告)号：US20190088546A1

公开(公告)日：2019-03-21

申请号：US16198546

申请日：2018-11-21

Applicant: SK hynix Inc.

Inventor： Jong Su KIM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53204 ,  H01L23/53295 ,  H01L23/5386

Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive to pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.

公开(公告)号：US20180102415A1

公开(公告)日：2018-04-12

申请号：US15716547

申请日：2017-09-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yanzheng ZHANG

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L29/45 ,  H01L21/283 ,  H01L21/823814 ,  H01L21/82385 ,  H01L23/53204 ,  H01L27/0922 ,  H01L29/417 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7827 ,  H01L2224/05 ,  H01L2224/48463

Abstract: A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.