公开(公告)号：US10466097B2

公开(公告)日：2019-11-05

申请号：US15843883

申请日：2017-12-15

Applicant: 3D Plus

Inventor： Didier Gambart

IPC: G01J1/02 ,  G01J1/42 ,  H01L27/146 ,  H04N5/225

Abstract: A 3D imaging optoelectronic module intended to be fixed to an image-forming device comprises: an optoelectronic sensor comprising a package with a chip electrically connected to a stack of at least one printed circuit board, the sensor and stack assembly molded in a resin and having faces according to Z with electrical interconnection tracks of the printed circuit boards. It comprises a thermally conductive rigid cradle in the form of a frame having a reference surface according to X, Y and: on a top surface: reference points intended to center and align the image-forming device in relation to the reference surface, fixing points to allow the fixing of the image-forming device, and an inner bearing surface having bearing points of the sensor adjusted to center and align the chip in relation to the reference surface.

公开(公告)号：US09899250B2

公开(公告)日：2018-02-20

申请号：US15621908

申请日：2017-06-13

Applicant: 3D PLUS

Inventor： Christian Val

IPC: H01L21/683 ,  H01L25/00 ,  H01L23/00 ,  H05K3/32

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/142 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/3511 ,  H05K3/321 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency comprises: a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to the following sub-steps in the following order: A1)) the electronic packages are placed on a first sticky skin, balls side, B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer, C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls, D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls, E1) thinning of the intermediate wafer on the balls side face, F1) formation of a balls side redistribution layer, G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the original thickness of the electronic packages, several reconstituted wafers having been obtained on completion of the previous sub-steps, stacking of the reconstituted wafers, dicing of the stacked reconstituted wafers to obtain 3D modules.

公开(公告)号：US20130344654A1

公开(公告)日：2013-12-26

申请号：US14003940

申请日：2012-03-06

Applicant: Olivier Limousin ,  Fabrice Soufflet

Inventor： Olivier Limousin ,  Fabrice Soufflet

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/27003 ,  H01L2224/2711 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/00013 ,  H01L2924/12042 ,  H05K3/027 ,  H05K3/06 ,  H05K3/12 ,  H05K3/321 ,  H05K3/4007 ,  H05K2201/10674 ,  H05K2203/107 ,  H05K2203/1476 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: The invention relates to a process for flip-chip connection of an electronic component (D) to a substrate (B), characterized in that it comprises producing at least one interconnect pad (PC) by etching a thick conductive film and bonding it, by means of at least one conductive adhesive, between a receiving pad or area of said electronic component and a receiving pad or area (PAS) of said substrate.

Abstract translation: 本发明涉及一种用于将电子元件（D）倒装连接到基板（B）的工艺，其特征在于，它包括通过蚀刻厚导电膜并将其粘接来制造至少一个互连焊盘（PC），通过 至少一种导电粘合剂的装置，在所述电子部件的接收垫或区域与所述基板的接收垫或区域（PAS）之间。

公开(公告)号：US08567051B2

公开(公告)日：2013-10-29

申请号：US12258060

申请日：2008-10-24

Applicant: Christian Val

Inventor： Christian Val

IPC: H01K3/10 ,  H05K3/30 ,  H05K3/10 ,  H05K3/02

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/351 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer.

Abstract translation: 一种用于3D电子模块（100）的垂直互连的方法，包括通过垂直于晶片平面的堆叠方向电连接在一起的K个电子晶片级（19）的堆叠的模块。

公开(公告)号：US08243468B2

公开(公告)日：2012-08-14

申请号：US11910433

申请日：2006-04-03

Applicant: Christian Val

Inventor： Christian Val

IPC: H01R12/16

CPC classification number: H01L23/4985 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/09663 ,  H05K2203/041 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00

Abstract: The invention relates to an electronic module comprising a stack of n packages of predetermined thickness E, which are provided on a lower surface with connection balls of predetermined thickness eb, said connection balls being connected to a printed circuit for interconnecting the package. The printed circuit is placed on the lower surface of the package level with the balls, is drilled with metallized holes, in which the balls are located and to which they are connected, and has a thickness eci less than eb so as to obtain a module with a total thickness not exceeding n (E+10% eb).

Abstract translation: 本发明涉及一种电子模块，其包括具有预定厚度E的n个封装的堆叠，其在具有预定厚度eb的连接球的下表面上提供，所述连接球连接到用于互连封装的印刷电路。 印刷电路被放置在具有滚珠的包装水平的下表面上，钻有金属化的孔，其中滚珠位于其中并且它们被连接，并且具有小于eb的厚度eci以获得模块 总厚度不超过n（E + 10％eb）。

公开(公告)号：US20120094439A1

公开(公告)日：2012-04-19

申请号：US13377109

申请日：2010-06-14

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L21/78

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer.

Abstract translation: 一种用于制造重构晶片的方法，其包括具有连接焊盘的芯片，包括：制造芯片的第一晶片，在所述晶片上制造堆叠的至少一层芯片焊盘重新分布的导电轨道 芯片的互连，该堆叠被指定为主RDL层，切割该晶片以获得各自配备有RDL层的各个芯片，将具有RDL层的各个芯片传递到足够刚性的支撑件，以在下列过程中保持平坦 步骤，该支撑件配备有粘合剂层，RDL层在粘合剂层上，沉积树脂以封装芯片，聚合树脂，去除刚性载体，按顺序沉积单个再分布层，称为小型RDL 将主RDL层的导电轨道连接到互连触点，通过在粘合剂层中制成的孔，晶片包括 聚合树脂，具有RDL层的芯片和小型RDL是重新构建的晶片。

公开(公告)号：US20210335755A1

公开(公告)日：2021-10-28

申请号：US17240789

申请日：2021-04-26

Applicant: 3D PLUS

Inventor： Christian VAL

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: The field of the invention is that of producing 3D electronic modules, compatible with components operating beyond 1 GHz. The invention relates to a 3D electronic module featuring an interconnection between a horizontal conductor and a vertical conductor to which it is connected exhibits, in a vertical plane, a non-zero curvature. It also relates to the associated production process.

公开(公告)号：US10930178B2

公开(公告)日：2021-02-23

申请号：US16704458

申请日：2019-12-05

Applicant: SOLUTION 3D PLUS INC.

Inventor： Michel Cournoyer

IPC: G09F3/02 ,  F16B1/00

Abstract: A system for sorting hardware pieces having first and second characteristics. The system comprises: a chart displaying first values associated with the first characteristic, each first value associated to a unique first graphical combination comprising a first-characteristic background motif and a first-characteristic indicium overlaid thereon; and second values associated with the second characteristic, each second value associated to a unique second graphical combination comprising a second-characteristic background motif and a second-characteristic indicium overlaid thereon; an identification label indicative of the first and second characteristics and comprising: a first section covered with a first graphical composition comprising the first graphical combination; and a second section covered with a second graphical composition comprising the second graphical combination; and a container affixed with the identification label for containing the hardware piece corresponding to the first and second characteristics.

公开(公告)号：US09111688B2

公开(公告)日：2015-08-18

申请号：US14115853

申请日：2012-05-04

Applicant: Christian Val

Inventor： Christian Val

IPC: H01G4/224 ,  H05K3/28 ,  H01L21/56 ,  H01L23/00 ,  C23C14/08 ,  C23C16/01 ,  C23C16/40 ,  B05D5/10 ,  B05D1/02 ,  H01L23/31 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01G4/224 ,  B05D1/02 ,  B05D5/10 ,  C23C14/08 ,  C23C16/01 ,  C23C16/402 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/18 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68368 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/181 ,  H05K3/284 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: A method for collectively fabricating a reconstituted wafer comprising chips exhibiting connection pads on a front face of the chip, comprises: positioning the chips on an initial adhesive support, front face on the support, vapor deposition at atmospheric pressure and ambient temperature, of an electrically insulating layer on the initial support and the chips, having a mechanical role of holding the chips, transfer of the chips covered with the mineral layer onto a provisional adhesive support, rear face of the chips toward this provisional adhesive support, removal of the initial adhesive support, overlaying the chips onto a support of “chuck” type, front faces of the chips toward this support, removal of the provisional adhesive support, deposition of a resin on the support of “chuck” type to encapsulate the chips, and then polymerization of the resin, removal of the support of “chuck” type, production of an RDL layer active face side.

Abstract translation: 一种用于共同制造重构的晶片的方法，其包括在芯片的前表面上显示连接焊盘的芯片，包括：将芯片定位在初始粘合剂支撑体上，支撑体上的正面，大气压和环境温度下的气相沉积 在初始支撑体上的绝缘层和芯片，具有保持芯片的机械作用，将由矿物层覆盖的芯片转移到临时粘合剂支撑体上，将芯片的后表面朝向该临时粘合剂支撑件移除，初始粘合剂的去除 支撑，将芯片叠加到“卡盘”型的支撑件上，朝向该支撑件的芯片的前表面，去除临时粘合剂支撑件，将树脂沉积在“卡盘”型支撑件上以封装芯片，然后聚合 的树脂，去除“卡盘”型的支撑，生产RDL层有源面。

公开(公告)号：US20100276081A1

公开(公告)日：2010-11-04

申请号：US12522426

申请日：2008-01-28

Applicant: Christian Val

Inventor： Christian Val

IPC: B32B37/00

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16146 ,  H01L2224/81224 ,  H01L2224/8184 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).

Abstract translation: 本发明涉及一种将第一晶片（T1）的电子部件与第二晶片（T2）的电子部件互连的方法，每个晶片具有在厚度方向上穿过晶片的金属化通孔（1）。 该方法包括在第一晶片（T1）的每个通孔（1）上沉积含有溶剂的导电油墨滴（3）; 在第一晶片（T1）的通孔（1）上基本上重叠第二晶片（T2）的第一晶片（T2）的堆叠，使得第二晶片（T2）的通孔（1） 通过加热或施加真空去除包含在液滴（3）中的50至90％的溶剂，以获得糊状油墨; 和糊状墨滴（3）的激光烧结，以在叠置的金属化通孔（1）之间产生电连接（31）。