公开(公告)号：US07635641B2

公开(公告)日：2009-12-22

申请号：US11250421

申请日：2005-10-17

Applicant: Dror Hurwitz ,  Mardechay Farkash ,  Eva Igner ,  Amit Zeidler ,  Boris Statnikov ,  Benny Michaeli

Inventor： Dror Hurwitz ,  Mardechay Farkash ,  Eva Igner ,  Amit Zeidler ,  Boris Statnikov ,  Benny Michaeli

IPC: H01L21/44

CPC classification number: H05K3/4647 ,  H01L21/4857 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/108 ,  H05K3/205 ,  H05K3/388 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2203/0152 ,  H05K2203/0384 ,  H05K2203/0733 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.

Abstract translation: 一种制造电子基板的方法，包括以下步骤： （A）选择第一基层; （B）在所述第一基底层上沉积第一耐蚀刻阻挡层; （C）建立交替导电层和绝缘层的前半层叠层，所述导电层通过绝缘层互连， （D）将第二基层施加到所述第一半叠层上; （F）将光致抗蚀剂的保护涂层施加到第二基层; （F）蚀刻掉第一基层; （G）去除光致抗蚀剂的保护涂层; （H）去除第一耐蚀刻阻挡层; （I）构建交替导电层和绝缘层的第二半叠层，所述导电层通过绝缘层互连，其中所述第二半堆叠具有基本对称的层叠到所述第一半堆叠; （J）将绝缘层施加到交替导电层和绝缘层的第二霍尔堆叠上，（K）去除第二基层，和（L）通过暴露堆叠的外表面上的通孔的端部并施加端接 到此。

公开(公告)号：US20070289127A1

公开(公告)日：2007-12-20

申请号：US11737269

申请日：2007-04-19

Applicant: Dror HURWITZ ,  Mordechay FARKASH ,  Eva IGNER ,  Boris STATNIKOV ,  Benny MICHAELI

Inventor： Dror HURWITZ ,  Mordechay FARKASH ,  Eva IGNER ,  Boris STATNIKOV ,  Benny MICHAELI

IPC: H01L21/48 ,  H01L21/02 ,  H01L23/538 ,  H01R12/02

CPC classification number: H01L21/4857 ,  H01L21/4864 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/183 ,  H05K3/06 ,  H05K3/205 ,  H05K3/4647 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

Abstract translation: 一种用于制造用于支撑与第二IC芯片串联连接的第一IC芯片的IC支架的方法; 所述IC支架包括一组交替的铜特征层和绝缘环绕的通孔，所述第一IC管芯可粘合到所述IC支架上，并且所述第二IC管芯可在所述IC支架内部的空腔内接合，其中所述空腔由 蚀刻铜基，并选择性地蚀刻掉铜层。

公开(公告)号：US07669320B2

公开(公告)日：2010-03-02

申请号：US11737269

申请日：2007-04-19

Applicant: Dror Hurwitz ,  Mordechay Farkash ,  Eva Igner ,  Boris Statnikov ,  Benny Michaeli

Inventor： Dror Hurwitz ,  Mordechay Farkash ,  Eva Igner ,  Boris Statnikov ,  Benny Michaeli

IPC: H05K3/10

CPC classification number: H01L21/4857 ,  H01L21/4864 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/183 ,  H05K3/06 ,  H05K3/205 ,  H05K3/4647 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

Abstract translation: 一种用于制造用于支撑与第二IC芯片串联连接的第一IC芯片的IC支架的方法; 所述IC支架包括一组交替的铜特征层和绝缘环绕的通孔，所述第一IC管芯可粘合到所述IC支架上，并且所述第二IC管芯可在所述IC支架内部的空腔内接合，其中所述空腔由 蚀刻铜基，并选择性地蚀刻掉铜层。