Abstract:
A plated wire memory according to the present disclosure includes a barrier layer disposed between a core of non-magnetic conductive material and an outer layer of highly permeable magnetic material, such as permalloy. The barrier layer is constructed of a conductive material which will not diffuse into the outer magnetic layer, an example of such material being gold or gold-copper alloy.
Abstract:
The present invention is a binary data manipulation network comprising a pair of mask generation networks in a configuration which controls a merge network to allow a first operand to be manipulated by insertion of selected bits from a second operand at a selected position. Each mask generation network produces a result operand consisting of a group of binary ones adjacent to a group of binary zeroes where the break point between ones and zeroes is determined by an input count operand. The two mask generation networks are connected to the merge network in end for end fashion so that, typically, the merge network gates the bits of the first operand as the result operand when the mask generation network result operands are dissimilar and gates the bits of the second operand when the bits of the mask generation network result operands are similar. The apparatus of the present invention also performs other related operations using the network configuration disclosed.
Abstract:
A demand driven multiplexing system is provided having first and second closed-loop communications links, each connected to a central control station and to a plurality of serially-arranged remote stations. The central station includes means adapted to issue an end-of-batch code on one link and each remote station includes means responsive to the end-of-batch code to remove the same from any data train on the link and insert a message thereon, followed by the end-of-batch code. The central station also issues data trains on the other link, each data group having an address code. Each remote station is responsive to the address code to copy the particular data group from the link.
Abstract:
Apparatus is provided for producing pulses synchronous with the phase and frequency of an unregulated alternating signal. An electrical bridge is provided having a pair of rectifiers and a pair of impedance devices forming the legs thereof. The unregulated signal is applied to the junction between the diodes and voltage-controlled clock means is connected to the junction between the impedance devices. The clock drives logic which provides positive and negative pulse train outputs whose rates are dependent upon the signal from the bridge, and returns the pulse trains to opposite sides of the bridge. If the pulse trains are out of frequency with the unregulated signal, the bridge becomes unbalanced in such a manner as to alter the frequency rate of the clock.
Abstract:
A system of driving a plasma display panel is disclosed using a pair of independently driven impedance devices coupled to each horizontal and vertical drive line and which requires a source of direct current operating through electronic switching devices associated with each impedance device to form a distributed driver matrix selection scheme for each display element in the panel.
Abstract:
An optical grating which has a preselected coefficient of thermal expansion can be made by attaching grating bars to a slotted plate having the desired coefficient of thermal expansion in a position making the bars visible through the slot. The grating bars are transverse to the slot and firmly bonded to its edges, and are carried by a transparent sheet whose effect on thermal expansion of the plate is negligible.
Abstract:
A pulse width modulator according to the present disclosure includes a circuit branch having an integrating device for transforming a signal value to a pulse width of predetermined time period. The integrating device includes a first differential amplifier having an inverting and a non-inverting input, and an output, with a storage device connected between the inverting input and the output of the first amplifier. A second differential amplifier has its inverting input connected to the output of the first amplifier, and has its output connected to a reset device to reset the storage device. One signal input is supplied to the inverting input of the first amplifier and another signal input is supplied to the non-inverting input of the second amplifier. The output is taken from the output of the second amplifier. According to a modification of the apparatus, a second branch is provided, similar to the first, and arranged such that second branch forms part of the reset device for the first branch, and vice versa.
Abstract:
An electronic circuit module is housed in a thermally conductive housing having fluid conduits therein for carrying coolant. The circuit module includes a stack of a plurality of circuit boards supported in the housing, each circuit board having a thermally conductive member attached to opposite side portions thereof, each member having a sawtooth edge portion. A cooling bar is sandwiched between a wall of the housing and the side members of the stack, and includes a surface adapted to abut the inner surface of the wall and a sawtooth portion of each member. Torque means, such as a threaded fastener, is provided for moving the cooling bar to wedge the same between the members and the wall to establish good thermal connection between the coolant in the fluid conduits and the circuit boards.
Abstract:
The synchronizing and data signals for the displaying of data on the face of a video display unit are multiplexed into one composite signal by the use of voltage summing apparatus. The composite signal is transmitted on a single coaxial cable to the remotely located display unit where the original signals are reconstructed by circuits sensitive to frequency, level, or both.
Abstract:
In a digital computer, a normalize shift count network is provided which operates on either positive or negative operands stored in a register. The shift count network operates in either a regular mode or a double operand mode where each of the two operands is one-half the regular width operand to produce as a result operand or operands the number of register positions the input operand or operands must be shifted in order to produce normalized operands. Initially the operand is examined by a rank of Exclusive OR circuits arranged so that, generally, each bit of the operand forms one input to two adjacent exclusive OR circuits and so that each exclusive OR circuit, in turn, receives its two independent input quantities from adjacent bits of the operand. The upper bit of the operand is the sign bit and forms one input to a first exclusive OR circuit. The sign bit also forms one input into a second exclusive OR circuit which has as its other input the first significant bit of the operand. The exclusive OR circuits determine where the first significant bit of the operand is located by the comparison of the first bit of the numerical portion of the operand with the sign bit and by subsequent comparison of each bit with the preceeding bit. The shift count for this first significant bit is decoded by examining the outputs of the exclusive OR circuits in a plurality of independent predetermined groups to independently define the individual bit values in a binary number expressing their required shift count for normalization.