Secure wear levelling of non-volatile memory based on Galois field circuit

    公开(公告)号:US12300295B2

    公开(公告)日:2025-05-13

    申请号:US17842329

    申请日:2022-06-16

    Abstract: Wear levelling techniques based on use of a Galois field for the logical to physical translation of data addresses for a non-volatile memory, such as an MRAM-based memory, are presented. This not only provides a wear levelling technique to extend memory life, but also adds an additional layer of security to the stored memory data. More specifically, the following presents embodiments for secure wear levelling based on a Galois field having an order based on the size of the memory. To further improve security, a randomly generated rotation of the logically address based on the Galois field can also be used.

    Apparatus and methods for smart verify with adaptive voltage offset

    公开(公告)号:US12293797B2

    公开(公告)日:2025-05-06

    申请号:US18355343

    申请日:2023-07-19

    Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

    Current reference circuit with process, voltage, and wide-range temperature compensation

    公开(公告)号:US12271217B2

    公开(公告)日:2025-04-08

    申请号:US17903464

    申请日:2022-09-06

    Abstract: Systems and methods are provided for generating a stable reference current that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners. In an example implementation, an improved reference current generator circuit is provided that includes a first circuit generating a first current that is proportional to absolute temperature and a second circuit generating a second current that is complementary to absolute temperature based on first transistors operating in respective triode regions. The second current compensates for process, voltage, and temperature variations in the first current at a node. According to some examples, the second current is also generated based on second transistors operating in respective saturation regions. The first current may be generated using a forward biased PN junction diode.

    Read schemes with adjustment for neighboring word line sanitization

    公开(公告)号:US12254218B2

    公开(公告)日:2025-03-18

    申请号:US18360252

    申请日:2023-07-27

    Abstract: An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

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