-
1.
公开(公告)号:US20200294582A1
公开(公告)日:2020-09-17
申请号:US16887306
申请日:2020-05-29
Applicant: Toshiba Memory Corporation , SanDisk Technologies LLC
Inventor: Tomoharu Tanaka , Jian Chen
IPC: G11C11/56 , G11C16/04 , G11C16/34 , H01L27/115 , H01L27/11521 , H01L27/11524 , G11C16/12 , G11C16/10
Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
-
公开(公告)号:US12300295B2
公开(公告)日:2025-05-13
申请号:US17842329
申请日:2022-06-16
Applicant: SanDisk Technologies LLC
Inventor: Martin Hassner , Mark Branstad
Abstract: Wear levelling techniques based on use of a Galois field for the logical to physical translation of data addresses for a non-volatile memory, such as an MRAM-based memory, are presented. This not only provides a wear levelling technique to extend memory life, but also adds an additional layer of security to the stored memory data. More specifically, the following presents embodiments for secure wear levelling based on a Galois field having an order based on the size of the memory. To further improve security, a randomly generated rotation of the logically address based on the Galois field can also be used.
-
公开(公告)号:US12293797B2
公开(公告)日:2025-05-06
申请号:US18355343
申请日:2023-07-19
Applicant: SanDisk Technologies LLC
Inventor: Longju Liu , Sarath Puthenthermadam , Jiahui Yuan
Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.
-
公开(公告)号:US12289886B2
公开(公告)日:2025-04-29
申请号:US17660278
申请日:2022-04-22
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Nao Nagase , Chiko Kudo , Tsutomu Imai
Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.
-
公开(公告)号:US12271217B2
公开(公告)日:2025-04-08
申请号:US17903464
申请日:2022-09-06
Applicant: SanDisk Technologies LLC
Inventor: Mohammad Reza Mahmoodi , Martin Lueker-Boden
Abstract: Systems and methods are provided for generating a stable reference current that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners. In an example implementation, an improved reference current generator circuit is provided that includes a first circuit generating a first current that is proportional to absolute temperature and a second circuit generating a second current that is complementary to absolute temperature based on first transistors operating in respective triode regions. The second current compensates for process, voltage, and temperature variations in the first current at a node. According to some examples, the second current is also generated based on second transistors operating in respective saturation regions. The first current may be generated using a forward biased PN junction diode.
-
公开(公告)号:US12270853B2
公开(公告)日:2025-04-08
申请号:US18221824
申请日:2023-07-13
Applicant: SanDisk Technologies LLC
Inventor: Toru Miwa , Takashi Murai , Hiroyuki Ogawa , Nisha Padattil Kuliyampattil
IPC: G01R31/28 , G01R1/073 , H01L21/66 , H01L23/522 , H01L25/065 , H01L23/00
Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.
-
公开(公告)号:US12256544B2
公开(公告)日:2025-03-18
申请号:US17682550
申请日:2022-02-28
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Kazuto Watanabe , Youko Furihata
Abstract: Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.
-
公开(公告)号:US12254218B2
公开(公告)日:2025-03-18
申请号:US18360252
申请日:2023-07-27
Applicant: SanDisk Technologies LLC
Inventor: Md Raquibuzzaman , Sujjatul Islam , Ravi J. Kumar
IPC: G06F3/06
Abstract: An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.
-
公开(公告)号:US12245434B2
公开(公告)日:2025-03-04
申请号:US17590278
申请日:2022-02-01
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Monica Titus , Roshan Jayakhar Tirukkonda , Senaka Kanakamedala , Raghuveer S. Makala
Abstract: A method includes forming an alternating stack of first and second layers, forming a composite hard mask layer over the alternating stack, forming openings in the hard mask, and forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the openings in the composite hard mask layer through the alternating stack. The compositing hard mask includes a first cladding material layer which has higher etch resistance than upper and lower patterning films of the composite hard mask.
-
公开(公告)号:US12243593B2
公开(公告)日:2025-03-04
申请号:US17685613
申请日:2022-03-03
Applicant: SanDisk Technologies LLC
Inventor: Xiang Yang , Deepanshu Dutta , Ohwon Kwon , James Kai , Yuki Mizutani
Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.
-
-
-
-
-
-
-
-
-