公开(公告)号：US07609117B2

公开(公告)日：2009-10-27

申请号：US10801482

申请日：2004-03-15

Applicant: Enrico Temporiti Milani ,  Guido Gabriele Albasini

Inventor： Enrico Temporiti Milani ,  Guido Gabriele Albasini

IPC: H03L7/00

CPC classification number: H03L7/1974 ,  H03L7/0891

Abstract: A phase-locked loop circuit is proposed for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit including means for deriving a feedback signal from the output signal, means for providing a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference. In the circuit of an embodiment of the invention, the means for causing the circuit to enter the lock condition includes means for conditioning the control signal to have an instantaneous value substantially zero in the lock condition by means of a conditioning signal consisting of a series of pulses each one corresponding to the pre-defined phase difference.

Abstract translation: 提出了一种锁相环电路，用于提供具有取决于参考信号的频率的频率的输出信号，该电路包括用于从输出信号导出反馈信号的装置，用于提供指示相位差的控制信号的装置 在参考信号和反馈信号之间，用于根据控制信号控制输出信号的频率的装置，以及用于当参考信号和反馈信号具有相同频率并使其前进时使电路进入锁定状态的装置 定义相位差。 在本发明的一个实施例的电路中，用于使电路进入锁定状态的装置包括用于调节控制信号以在锁定状态下具有基本为零的瞬时值的装置，该调节信号由一系列 每个脉冲对应于预定义的相位差。

公开(公告)号：US20040170062A1

公开(公告)日：2004-09-02

申请号：US10729875

申请日：2003-12-05

Applicant: STMICROELCTRONICS S.r.l ,  AGRATE BRIANZA, ITALY

Inventor： Rino Micheloni ,  Roberto Ravasio ,  Salvatrice Scommegna

IPC: G11C011/34 ,  G11C016/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1-MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state (405;507a,509c,513c); and repeats the steps of accessing and applying for the memory cells in the group whose programming state is not ascertained (411;509b,513b). After the programming state of a prescribed number of memory cells in the group has been ascertained, the memory cells in the group are accessed again and the programming state of the memory cells whose programming state was previously ascertained is re-ascertained (413,415;515). At least one additional programming pulse is applied to those memory cells in the group whose programming state is not re-ascertained (405;507a,509c,513c). The method guarantees that the programming state of the memory cells is ascertained in conditions that closely resembles, or are substantially identical, to the conditions in which the memory cells will be accessed in a standard read.

Abstract translation: 用于编程电可编程存储器的装置和方法访问存储器的一组存储器单元（MC1-MCK）以确定其编程状态（401,407; 503,509a，513a）; 对编程状态未确定的组中的那些存储单元施加编程脉冲以对应于期望的编程状态（405; 507a，509c，513c）; 并重复访问和应用编程状态未确定的组中的存储单元的步骤（411; 509b，513b）。 在已经确定组中规定数量的存储单元的编程状态之后，再次访问组中的存储单元，并且重新确定编程状态被预先确定的存储单元的编程状态（413,415; 515） 。 至少一个附加编程脉冲被施加到编程状态未被重新确定的组（405; 507a，509c，513c）中的那些存储器单元。 该方法确保在与标准读取存储器单元访问的条件非常相似或基本相同的条件下确定存储器单元的编程状态。

公开(公告)号：US5942936A

公开(公告)日：1999-08-24

申请号：US777418

申请日：1996-12-30

Applicant: Bruno Ricco ,  Massimo Lanzoni

Inventor： Bruno Ricco ,  Massimo Lanzoni

IPC: H03F1/30 ,  H03F3/45

CPC classification number: H03F1/303 ,  H03F3/45479

Abstract: To compensate the offset of a differential stage, the stage has at least one programmable, floating gate transistor with a programmable threshold, which is initially set to a threshold level other than the required threshold value, so that the differential stage is initially unbalanced. A balance input voltage is applied to the inputs of the differential stage. A programming voltage is applied to the programmable transistor to modify the set threshold until the differential stage switches. Upon switching, the programming voltage is cut off immediately, so that the charge required for the differential stage to be balanced with a balance input voltage is memorized in the programmable transistor.

Abstract translation: 为了补偿差分级的偏移，级具有至少一个可编程的具有可编程阈值的可编程浮置晶体管，其可初始设置为除所需阈值之外的阈值电平，使得差分级初始不平衡。 平衡输入电压施加到差动级的输入端。 编程电压被施加到可编程晶体管，以修改设定的阈值直到差分级开关。 在切换时，编程电压立即被切断，使得差分级与平衡输入电压平衡所需的电荷被存储在可编程晶体管中。

公开(公告)号：US09219408B2

公开(公告)日：2015-12-22

申请号：US14321600

申请日：2014-07-01

Applicant: DORA S.p.A.

Inventor： Alberto Bianco

IPC: H02M3/156 ,  H02M1/42

CPC classification number: H02M1/4225 ,  H02M1/4208 ,  Y02B70/126

Abstract: A transition mode power factor correction converter comprising a boost inductor, a switch, a diode, and output tank capacitor, has circuit means of limitation of the off-time interval of the switch to a fraction of the off-time interval, “complementary” to the on-time interval that is normally controlled for regulating the output voltage, during part of a cycle of a rectified sinusoidal voltage waveform input to the converter, when the current flowing in the inductor reaches a maximum threshold, causing the mode of operation of the device to switch from transition mode to continuous current mode for a middle phase angle region of a rectified sinusoidal input voltage waveform, under high load conditions, defined by said maximum current threshold. Current peaks amplitude and ripple are effectively reduced for same output power.

Abstract translation: 包括升压电感器，开关，二极管和输出电容器的过渡模式功率因数校正转换器具有将开关的截止时间间隔限制到关断时间间隔的一部分的电路装置，“互补” 在输入到转换器的整流正弦波电压波形的一部分周期期间，当电流中流过电感器的电流达到最大阈值时，通常被控制用于调节输出电压的导通时间间隔，导致操作模式 在由最大电流阈值定义的高负载条件下，整流正弦输入电压波形的中间相位角的转换模式切换到连续电流模式。 对于相同的输出功率，电流峰值幅度和纹波有效降低。