-
公开(公告)号：US12197889B2
公开(公告)日：2025-01-14
申请号：US17352374
申请日：2021-06-21
Applicant: Ceremorphic, Inc.
Inventor： Dylan Finch
Abstract: A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates: an integer form fraction at a first bitwidth and a second bitwidth greater than the first bitwidth, a sign bit, and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. The integer form fractions of the first bitwidths are provided to an adder tree using the first bitwidth, and if the sum has an excess percentage of leading 0s, then the second bitwidth is used by an adder tree using the second bitwidth to form a great precision integer form fraction. The sign, integer form fraction, and maximum exponent are provided to an normalizer which generates a floating point result.
-
公开(公告)号：US12118331B2
公开(公告)日：2024-10-15
申请号：US17163588
申请日：2021-02-01
Applicant: Ceremorphic, Inc.
Inventor： Martin Kraemer , Ryan Boesch , Wei Xiong
CPC classification number: G06F7/5443 , G06F17/16 , H03K19/20 , H03M1/38
Abstract: A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.
-
公开(公告)号：US12105625B2
公开(公告)日：2024-10-01
申请号：US17588240
申请日：2022-01-29
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Venkat Mattela , Heonchul Park
IPC: G06F12/04 , G06N3/0464 , G06N3/10
CPC classification number: G06F12/04 , G06N3/0464 , G06N3/10 , G06F2212/16
Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
-
公开(公告)号：US12072799B2
公开(公告)日：2024-08-27
申请号：US18121294
申请日：2023-03-14
Applicant: CEREMORPHIC, INC.
Inventor： Lizy Kurian John , Venkat Mattela , Heonchul Park
IPC: G06F12/04 , G06N3/0464 , G06N3/10
CPC classification number: G06F12/04 , G06N3/0464 , G06N3/10 , G06F2212/16
Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
-
公开(公告)号：US12045645B2
公开(公告)日：2024-07-23
申请号：US16945871
申请日：2020-08-02
Applicant: Silicon Laboratories Inc.
IPC: G06F9/48 , G06F9/30 , G06F9/38 , G06F9/50 , H04L49/90 , H04L65/60 , H04W4/80 , H04W12/06 , H04W80/02 , H04W80/04
CPC classification number: G06F9/4812 , G06F9/30101 , G06F9/3822 , G06F9/3836 , G06F9/5061 , H04L49/90 , H04L65/60 , H04W4/80 , H04W12/06 , H04W80/02 , H04W80/04
Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.
-
Patent Agency Ranking
公开(公告)号：US11983537B1
公开(公告)日：2024-05-14
申请号：US18086458
申请日：2022-12-21
Applicant: CEREMORPHIC, INC.
Inventor： Venkat Mattela , Heonchul Park , Radhika Ponnamaneni , Govardhan Mattela
CPC classification number: G06F9/3802 , G06F9/30101 , G06F9/382 , G06F9/3851 , G06F9/3873
Abstract: A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.
-
公开(公告)号：US11983237B2
公开(公告)日：2024-05-14
申请号：US17180831
申请日：2021-02-21
Applicant: Redpine Signals, Inc.
Inventor： Dylan Finch
CPC classification number: G06F17/16 , G06F7/483 , G06F7/5443
Abstract: A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.
-
公开(公告)号：US11977936B2
公开(公告)日：2024-05-07
申请号：US17139945
申请日：2020-12-31
Applicant: Ceremorphic, Inc.
Inventor： Martin Kraemer , Ryan Boesch , Wei Xiong
CPC classification number: G06G7/16 , G06F7/5443
Abstract: A differential multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to respective positive and negative unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. Each positive and negative unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each positive and negative unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors and to an analog to digital converter to generate a digital output product. The charge transfer lines may span multiple unit elements.
-
公开(公告)号：US11953389B2
公开(公告)日：2024-04-09
申请号：US17190390
申请日：2021-03-02
Applicant: Intelligent Fiber Optic Systems Corporation
Inventor： Behzad Moslehi , Mehrdad Moslehi
IPC: G01L1/24 , G01D5/353 , G01K11/3206
CPC classification number: G01L1/246 , G01D5/35387 , G01K11/3206
Abstract: An optical sensing system including an optical interrogator is operative with an array of reflective sensors, each sensor providing a separable reflected spectral response parameter such as a unique Gaussian standard deviation or reflected response compared to other sensors in the same operating wavelength range. The optical interrogator provides narrowband swept or broadband continuous optical power source to the array of FBG sensors, and an optical interrogator generates a g(x) representation of power vs wavelength of the reflected optical power and decomposes the representation into the wavelength of the individual sensors, thereby allowing operation of two or more FBG sensors in the same operating wavelength range.
-
公开(公告)号：US11916679B2
公开(公告)日：2024-02-27
申请号：US17006532
申请日：2020-08-28
Applicant: Silicon Laboratories Inc.
Inventor： Sriram Mudulodu , Divyaxi Rudani , Manoj Medam , Partha Sarathy Murali , Ajay Mantha , Suchin Gupta
IPC: H04L1/1812 , H04L25/03 , H04W4/80
CPC classification number: H04L1/1819 , H04L1/1816 , H04L25/03866 , H04W4/80
Abstract: A bitstream modifier is operative on a packet which uses repetition coding. The bitstream modifier increases randomness of the data in a deterministic manner such that spectral spurs from repetition coding are greatly reduced, thereby providing greater available transmit power. In another example of the invention, baseband samples of a header and/or payload for a Bluetooth packet are modified by a canonical sequence with a low slew rate for data such that the variations in frequency may be tracked by a receiver and the transmitted spectral spurs reduced.
-
-
-
-
-
-
-
-
-
Search Results
267
records
(took 0.017 seconds)
