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    ADJUSTMENT OF FPGA SYSTEM DESIGN USING LANGUAGE-BASED MACHINE LEARNING MODELS
    3.
    发明申请
    ADJUSTMENT OF FPGA SYSTEM DESIGN USING LANGUAGE-BASED MACHINE LEARNING MODELS 有权

    公开(公告)号：US20250013823A1

    公开(公告)日：2025-01-09

    申请号：US18896267

    申请日：2024-09-25

    Applicant: Altera Corporation

    Inventor： Kuan Woei Lam ,  Chew Yee Kee ,  Zhi Chuan Yip

    IPC: G06F40/274 ,  G06F30/33

    Abstract: Systems or methods of the present disclosure may provide systems and methods for adjusting a system design for a field-programmable gate array (FPGA) in response to a compilation error based on one or more language-based machine learning (ML) models trained on error messages of prior system designs. A method may include receiving an error message associated with a system design of an FPGA, generating a language-based machine learning (ML) prompt based at least on the error message, and determining an adjustment to the system design based on providing the language-based ML prompt to one or more language-based ML models trained on prior error messages.

    Techniques For Testing Leakage Current In Input And Output Circuits
    4.
    发明申请
    Techniques For Testing Leakage Current In Input And Output Circuits 有权

    公开(公告)号：US20240402245A1

    公开(公告)日：2024-12-05

    申请号：US18800444

    申请日：2024-08-12

    Applicant: Altera Corporation

    Inventor： Chiew Khiang Kuit ,  Ching Sia Lim ,  Ann Poh Gan

    IPC: G01R31/28

    Abstract: An integrated circuit includes an output circuit. The output circuit includes first, second, and third external contacts, a first output buffer circuit coupled to the first external contact, a first resistive circuit coupled between the first external contact and the second external contact, a second output buffer circuit coupled to the third external contact, and a second resistive circuit coupled between the second external contact and the third external contact. The output circuit has a test mode of operation to test for leakage current on the first and the third external contacts in response to receiving a first voltage applied externally to the first and the second resistive circuits through the second external contact. The output circuit has a user mode of operation wherein a supply voltage is applied externally to the first and the second resistive circuits through the second external contact.

    Adaptive Decision Feedback Equalization Tuning
    5.
    发明公开
    Adaptive Decision Feedback Equalization Tuning 审中-公开

    公开(公告)号：US20240235902A1

    公开(公告)日：2024-07-11

    申请号：US18617467

    申请日：2024-03-26

    Applicant: Altera Corporation

    Inventor： Mitchell Cooke

    IPC: H04L25/03

    CPC classification number: H04L25/03057 ,  H04L25/03267

    Abstract: A device of the present disclosure may include interface circuitry and a decision feedback equalization (DFE) tuner. The interface circuitry may be coupled to DFE circuitry by data interconnect. The DFE tuner may control adaptation of the DFE circuitry to a channel associated with the data interconnect using an oscillating reference voltage provided to the DFE circuitry. The interface circuitry may be coupled between the DFE tuner and the DFE circuitry.

    Scalable 2.5D interface circuitry
    8.
    发明授权
    Scalable 2.5D interface circuitry 有权

    公开(公告)号：US11741042B2

    公开(公告)日：2023-08-29

    申请号：US17561917

    申请日：2021-12-24

    Applicant: Altera Corporation

    Inventor： Chee Hak Teh ,  Arifur Rahman

    IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

    CPC classification number: G06F15/7803 ,  G06F1/06 ,  G06F1/10 ,  G06F13/4022 ,  G06F13/4234 ,  G06F13/4291 ,  G06F15/7864 ,  Y02D10/00

    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

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