公开(公告)号：US20120256722A1

公开(公告)日：2012-10-11

申请号：US13082444

申请日：2011-04-08

Applicant: Ashwinkumar C. Bhatt ,  Norman A. Card ,  Charles Buchter

Inventor： Ashwinkumar C. Bhatt ,  Norman A. Card ,  Charles Buchter

IPC: H01C1/02 ,  H01C17/00

CPC classification number: H01C7/003 ,  H01C1/028 ,  H01C17/02 ,  H01C17/06 ,  H05K1/167 ,  H05K2201/0187 ,  Y10T29/49082

Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.

Abstract translation: 在使用两个玻璃浸渍介电层的电子封装的空腔内形成埋入电阻器的方法，一个具有间隙孔，第二个具有电阻芯，该间隙放置在电阻器芯上并且组件熔接。 电阻芯周围剩余的空间填充有焊膏材料，组件用金属涂覆。 钻孔，清洁和电镀穿孔，然后蚀刻金属涂层并部分去除。 然后去除焊接掩模，并将一层镀金施加到暴露的金属表面。 使用玻璃浸渍的电介质层和熔融结合消除了与先前埋入的电阻器腔组件相关的氟化乙烯丙烯树脂（FEP）泄漏问题。

公开(公告)号：US06740819B2

公开(公告)日：2004-05-25

申请号：US10421272

申请日：2003-04-23

Applicant: Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

Inventor： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

IPC: H05K706

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/4641 ,  H05K2203/143

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract translation: 通孔形成在导电电力平面中。 可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。 没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。 开发人员用于去除任何未固化的PID材料。 包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。 在另一实施例中，动力平面具有从两侧施加的PID材料。 将光掩模应用于电源平面，通孔中的PID材料用光能固化。 开发人员用于清除未固化的PID材料。 如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。

公开(公告)号：US06608757B1

公开(公告)日：2003-08-19

申请号：US10101277

申请日：2002-03-18

Applicant: Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

Inventor： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

IPC: H05K716

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/4641 ,  H05K2203/143

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract translation: 通孔形成在导电电力平面中。 可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。 没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。 开发人员用于去除任何未固化的PID材料。 包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。 在另一实施例中，动力平面具有从两侧施加的PID材料。 将光掩模应用于电源平面，通孔中的PID材料用光能固化。 开发人员用于清除未固化的PID材料。 如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。

公开(公告)号：US5566448A

公开(公告)日：1996-10-22

申请号：US470389

申请日：1995-06-06

Applicant: Ashwinkumar C. Bhatt ,  Thomas P. Duffy ,  Jeffrey A. Knight ,  James P. Walsh

Inventor： Ashwinkumar C. Bhatt ,  Thomas P. Duffy ,  Jeffrey A. Knight ,  James P. Walsh

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H05K3/34

CPC classification number: H01L23/5385 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49833 ,  H01L2224/48091 ,  H01L2224/48227 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of forming an I/C chip mounting module, and for mounting an I/C chip thereon, is disclosed. A rigid cap and substrate are provided. A bottomed cavity is routed in the cap, and the substrate has circuitry formed thereon. The cap and substrate are laminated together with bond pads, which connect to the circuitry being disposed in the cavity. After circuitization of the exposed surface of the cap and drilling and plating of vias, the material of the cap overlying the cavity is removed to expose the bond pads. Thereafter, an I/C chip is connect to the pads.

Abstract translation: 公开了一种形成I / C芯片安装模块和用于在其上安装I / C芯片的方法。 提供了刚性帽和衬底。 有底的空腔在盖中布线，并且基板具有形成在其上的电路。 帽和衬底与连接到设置在空腔中的电路连接的接合焊盘层压在一起。 在盖的暴露表面电路化和通孔的钻孔和电镀之后，去除覆盖空腔的盖的材料以露出接合焊盘。 此后，I / C芯片连接到焊盘。

公开(公告)号：US5268260A

公开(公告)日：1993-12-07

申请号：US781542

申请日：1991-10-22

Applicant: Nageshwer R. Bantu ,  Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Joseph A. Kotylo ,  Gerald W. Jones ,  Robert J. Owen ,  Kostas Papathomas ,  Anaya K. Vardya

Inventor： Nageshwer R. Bantu ,  Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Joseph A. Kotylo ,  Gerald W. Jones ,  Robert J. Owen ,  Kostas Papathomas ,  Anaya K. Vardya

IPC: G03F7/32 ,  G03F7/42 ,  H05K3/06 ,  G03F7/30

CPC classification number: G03F7/422 ,  G03F7/325

Abstract: Simple, environmentally friendly developers and strippers are disclosed for free radical-initiated, addition polymerizable resists, cationically cured resists and solder masks and Vacrel photoresists. In all cases both the developers and the strippers include gamma butyrolactone, propylene carbonate and benzyl alcohol, optionally also including a minor amount of methanol, ethanol, isopropyl alcohol, propylene glycol monomethylacetate, ethylene glycol monomethyl ether, formamide, nitromethane, propylene oxide, or methyl ethyl ketone, acetone and water.

Abstract translation: 公开了简单的，环保的显影剂和剥离剂，用于自由基引发的可加聚合的抗蚀剂，阳离子固化的抗蚀剂和焊接掩模以及Vacrel光致抗蚀剂。 在所有情况下，显影剂和剥离剂都包括γ-丁内酯，碳酸亚丙酯和苄醇，任选地还包括少量甲醇，乙醇，异丙醇，丙二醇单甲基乙酸酯，乙二醇单甲醚，甲酰胺，硝基甲烷，环氧丙烷或 甲基乙基酮，丙酮和水。

公开(公告)号：US08493173B2

公开(公告)日：2013-07-23

申请号：US13082444

申请日：2011-04-08

Applicant: Ashwinkumar C. Bhatt ,  Norman A. Card ,  Charles Buchter

Inventor： Ashwinkumar C. Bhatt ,  Norman A. Card ,  Charles Buchter

IPC: H01C1/02

CPC classification number: H01C7/003 ,  H01C1/028 ,  H01C17/02 ,  H01C17/06 ,  H05K1/167 ,  H05K2201/0187 ,  Y10T29/49082

Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.

Abstract translation: 在使用两个玻璃浸渍介电层的电子封装的空腔内形成埋入电阻器的方法，一个具有间隙孔，第二个具有电阻芯，该间隙放置在电阻器芯上并且组件熔接。 电阻芯周围剩余的空间填充有焊膏材料，组件用金属涂覆。 钻孔，清洁和电镀穿孔，然后蚀刻金属涂层并部分去除。 然后去除焊接掩模，并将一层镀金施加到暴露的金属表面。 使用玻璃浸渍的电介质层和熔融结合消除了与先前埋入的电阻器腔组件相关的氟化乙烯丙烯树脂（FEP）泄漏问题。

公开(公告)号：US6009620A

公开(公告)日：2000-01-04

申请号：US115715

申请日：1998-07-15

Applicant: Ashwinkumar C. Bhatt ,  Joseph A. Kotylo ,  Kenneth S. Lyjak ,  Amarjit S. Rai ,  John A. Welsh

Inventor： Ashwinkumar C. Bhatt ,  Joseph A. Kotylo ,  Kenneth S. Lyjak ,  Amarjit S. Rai ,  John A. Welsh

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K3/0094 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/112 ,  H05K2201/0959 ,  H05K2203/0278 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of making a circuitized substrate wherein fill material is forced into the substrate's holes to thus provide additional support for conductive circuitry or the like thereon, thus increasing the final product's circuit density. The fill is provided in a substantially uncured state, following which partial cure occurs. Thereafter, the fill is substantially fully cured and the aforementioned circuit elements may then be provided directly thereon. Alternatively, a dual fill process is used with both quantities of uncured fill being disposed in each hole and then cured by a singular UV exposure step.

Abstract translation: 一种制造电路化基板的方法，其中填充材料被迫进入基板的孔中，从而为其上的导电电路等提供额外的支撑，从而增加最终产品的电路密度。 填充物以基本上未固化的状态提供，随后发生部分固化。 此后，填充物基本上完全固化，然后可以直接在其上提供上述电路元件。 或者，使用双填充方法，将两种量的未固化填料置于每个孔中，然后通过单一的UV曝光步骤固化。

公开(公告)号：US07510324B2

公开(公告)日：2009-03-31

申请号：US11882473

申请日：2007-08-02

Applicant: Ashwinkumar C. Bhatt ,  Varaprasad V. Calmidi ,  James J. McNamara, Jr. ,  Sanjeev Sathe

Inventor： Ashwinkumar C. Bhatt ,  Varaprasad V. Calmidi ,  James J. McNamara, Jr. ,  Sanjeev Sathe

IPC: H01J35/12

CPC classification number: G01N23/046 ,  G01N2223/419

Abstract: A method of inspecting articles using an imaging inspection apparatus which utilizes a plurality of individual imaging devices for directing beams onto the articles having objects therein to detect the objects based on established criteria. The method involves the enhanced cooling of the heat-generating imaging devices in which a fan directs cooling fluid onto a plurality of deflectors which in turn direct said fluid onto selected ones of said imaging devices.

Abstract translation: 使用成像检查装置检查制品的方法，所述成像检查装置利用多个单独的成像装置将光束引导到其上具有物体的物品上，以根据建立的标准检测物体。 该方法涉及对发热成像装置进行增强的冷却，其中风扇将冷却流体引导到多个偏转器上，反过来将导流体引导到所选择的成像装置上。

公开(公告)号：US20080168651A1

公开(公告)日：2008-07-17

申请号：US11652633

申请日：2007-01-12

Applicant: Ashwinkumar C. Bhatt ,  Robert J. Harendza ,  Robert M. Japp

Inventor： Ashwinkumar C. Bhatt ,  Robert J. Harendza ,  Robert M. Japp

IPC: H05K3/36

CPC classification number: H05K1/117 ,  H05K1/112 ,  H05K3/4611 ,  H05K2201/09127 ,  H05K2201/0919 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2203/061 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.

Abstract translation: 制造印刷电路板的方法，其中至少三个基板被对准并结合在一起（例如，使用层压）。 两个基板具有形成在其中的开口，每个开口包括位于其中的盖构件。 在层压期间，用于密封和防止介电材料（例如树脂）的盖构件在层压期间液化以接触内（第一）衬底的相对表面上的导电层。 因此，PCB在其中形成有突出边缘部分或多个空腔，使得可以使用边缘连接器等对PCB进行电连接。

公开(公告)号：US07354197B2

公开(公告)日：2008-04-08

申请号：US11141494

申请日：2005-06-01

Applicant: Ashwinkumar C. Bhatt ,  Varaprasad V. Calmidi ,  James J. McNamara, Jr. ,  Sanjeev Sathe

Inventor： Ashwinkumar C. Bhatt ,  Varaprasad V. Calmidi ,  James J. McNamara, Jr. ,  Sanjeev Sathe

IPC: H01J35/10 ,  H01J35/12 ,  H05G1/02 ,  G01N23/083

CPC classification number: G01N23/046 ,  G01N2223/3103 ,  G01N2223/419 ,  G01N2223/643 ,  H01J2235/1262

Abstract: An imaging inspection apparatus which utilizes a plurality of individual imaging devices (e.g., X-ray Computer Tomography scanning devices) positioned on a frame for directing beams onto articles having objects therein to detect the objects based on established criteria. The apparatus utilizes a cooling structure to provide cooling to the imaging devices.

Abstract translation: 一种成像检查装置，其利用位于框架上的多个单独的成像装置（例如，X射线计算机断层摄影扫描装置），用于将光束引导到具有其中的物体的物品上，以根据建立的标准检测物体。 该装置利用冷却结构为成像装置提供冷却。