公开(公告)号：US20250157970A1

公开(公告)日：2025-05-15

申请号：US18932755

申请日：2024-10-31

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Kung-Tzu Tu ,  Gwo-Shyan Sheu ,  Hsin-Hao Huang ,  Kuo-Liang Huang ,  Pei-Wen Wang ,  Yu-Chen Ma

IPC: H01L23/00 ,  H01L23/498

Abstract: A flip chip structure includes a circuit board and a chip. The circuit board includes first inner leads and second inner leads, each of the first inner leads has a first bonding portion, each of the second inner leads has a second bonding portion and a connecting segment. An included angle exists between the second bonding portion and the connecting segment, and an included angle exists between center lines of the first and second bonding portions. The chip includes first bumps and second bumps, and an included angle exists between center lines of the first and second bumps. Each of the first bumps is bonded to the first bonding portion, and each of the second bumps is bonded to the second bonding portion and the connecting segment to avoid bonding shift between the inner leads and the bumps or lessen bonding shift.

公开(公告)号：US20250071895A1

公开(公告)日：2025-02-27

申请号：US18768605

申请日：2024-07-10

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Hsiung Hu ,  Chun-Te Lee ,  Shyh-Jen Guo

IPC: H05K1/03

Abstract: A flexible circuit tape includes flexible circuit boards each including a substrate unit and a circuit unit. The circuit unit is disposed on a routing region of the substrate unit and includes circuit lines each having an inner lead and an outer lead. A second width between the two outermost outer leads accounts for 60.00-99.00% of a first width of the substrate unit. The first width is greater than or equal to 80 mm such that number of outer leads can be increased.

公开(公告)号：US12089326B2

公开(公告)日：2024-09-10

申请号：US17741543

申请日：2022-05-11

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yin-Chen Lin ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0298 ,  H05K1/115 ,  H05K1/118 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/10674

Abstract: A double-sided flexible circuit board includes a flexible substrate, through circuit lines, first circuit lines and second circuit lines. The first circuit lines are formed on a top surface of the flexible substrate and each includes a first segment, a bent segment and a second segment. One end of the first segment is connected to a first connection end of one of the through circuit lines. Both ends of the bent segment are connected to the other end of the first segment and one end of the second segment, respectively. A second distance between the adjacent second segments is greater than a first distance between the adjacent first segments. The second circuit lines are formed on a bottom surface of the flexible substrate and each is connected to a second connection end of one of the through circuit lines.

公开(公告)号：US20240194646A1

公开(公告)日：2024-06-13

申请号：US18374725

申请日：2023-09-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chen-Yu Wang ,  Chih-Hao Chiang ,  Pai-Sheng Cheng ,  Kung-An Lin ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Wen-Cheng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/13541 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

公开(公告)号：US20240008171A1

公开(公告)日：2024-01-04

申请号：US18143133

申请日：2023-05-04

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Wei-Teng Lin ,  Hui-Yu Huang ,  Ching-Chi Chan ,  Shih-Chieh Chang

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H05K1/0272 ,  H01L24/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/32225 ,  H01L2224/26175 ,  H01L2924/15151

Abstract: A semiconductor package includes a chip, a circuit board and a filling material. The circuit board includes a substrate, a patterned metal layer and a protective layer. A circuit area, a chip-mounting area and a flow-guiding area are defined on a surface of the substrate. The chip is mounted on the chip-mounting area. A flow-guiding member of the patterned metal layer is arranged on the flow-guiding area and includes a hollow portion and flow-guiding grooves which are communicated with the hollow portion and arranged radially. The flow-guiding grooves are provided to allow the protective layer to flow toward the hollow portion, and the hollow portion and the flow-guiding grooves are provided to allow the filling material to flow toward the protective layer such that the filling material can cover the protective layer to improve structural strength of the semiconductor package.

公开(公告)号：US11812554B2

公开(公告)日：2023-11-07

申请号：US17227458

申请日：2021-04-12

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yu-Chen Ma ,  Hsin-Hao Huang ,  Wen-Fu Chou ,  Gwo-Shyan Sheu

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/118 ,  H05K1/189 ,  H05K2201/0979 ,  H05K2201/09445 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.

公开(公告)号：US11602047B2

公开(公告)日：2023-03-07

申请号：US17380121

申请日：2021-07-20

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yin-Chen Lin ,  Ming-Hsiao Ke ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

IPC: H05K1/03 ,  H05K13/02 ,  H05K13/04

Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.

公开(公告)号：US20220336233A1

公开(公告)日：2022-10-20

申请号：US17856039

申请日：2022-07-01

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu ,  Fei-Jain Wu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

公开(公告)号：US20220210899A1

公开(公告)日：2022-06-30

申请号：US17512804

申请日：2021-10-28

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Tzu-Long Chuang ,  Hsin-Chieh Chuang ,  Chia-Hsin Hsiao ,  Tung-Li Tsai

IPC: H05F3/02

Abstract: A grounding structure includes a flexible conductive webbing and a counterweight disposed on the flexible conductive webbing. The flexible conductive webbing is weaved from conductive wires, provided to be mounted on a carrier and electrically connected to the carrier. The counterweight is used to allow the flexible conductive webbing to contact a ground in a way of surface contact for electrostatic discharge.

公开(公告)号：US20220110209A1

公开(公告)日：2022-04-07

申请号：US17470038

申请日：2021-09-09

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shih-Chieh Chang ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/14

Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.