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    Management of ownership control and data movement in shared-memory systems
    2.
    发明授权
    Management of ownership control and data movement in shared-memory systems 有权
    共享内存系统中的所有权控制和数据移动管理

    公开(公告)号：US08949549B2

    公开(公告)日：2015-02-03

    申请号：US12324628

    申请日：2008-11-26

    Applicant: David T. Harper, III ,  Charles David Callahan, II

    Inventor： David T. Harper, III ,  Charles David Callahan, II

    IPC: G06F12/00 ,  G06F3/00 ,  G06F9/00 ,  G06F9/52 ,  G06F12/08 ,  G06F3/06

    CPC classification number: G06F9/526 ,  G06F3/067 ,  G06F12/0813

    Abstract: A method to exchange data in a shared memory system includes the use of a buffer in communication with a producer processor and a consumer processor. The cache data is temporarily stored in the buffer. The method includes for the consumer and the producer to indicate intent to acquire ownership of the buffer. In response to the indication of intent, the producer, consumer, buffer are prepared for the access. If the consumer intends to acquire the buffer, the producer places the cache data into the buffer. If the producer intends to acquire the buffer, the consumer removes the cache data from the buffer. The access to the buffer, however, is delayed until the producer, consumer, and the buffer are prepared.

    Abstract translation: 在共享存储器系统中交换数据的方法包括使用与生产者处理器和消费者处理器进行通信的缓冲器。 高速缓存数据临时存储在缓冲区中。 该方法包括为消费者和生产者指示获取缓冲器所有权的意图。 响应于意图的指示，生产者，消费者，缓冲区准备进行访问。 如果消费者想要获取缓冲区，生产者将缓存数据放入缓冲区。 如果生产者打算获取缓冲区，消费者将从缓冲区中删除缓存数据。 然而，缓冲区的访问被延迟，直到生产者，消费者和缓冲区被准备好。

    REPRESENTATION AND MANIPULATION OF ERRORS IN NUMERIC ARRAYS
    3.
    发明申请
    REPRESENTATION AND MANIPULATION OF ERRORS IN NUMERIC ARRAYS 有权
    数字阵列中错误的表示和处理

    公开(公告)号：US20130132783A1

    公开(公告)日：2013-05-23

    申请号：US13300382

    申请日：2011-11-18

    Applicant: Sudarshan Raghunathan ,  C. David Callahan, II ,  Adam P. Jenkins

    Inventor： Sudarshan Raghunathan ,  C. David Callahan, II ,  Adam P. Jenkins

    IPC: G06F11/07

    CPC classification number: G06F11/0775

    Abstract: In an embodiment, a computer system accesses various different data entries in dense data array, where at least one of those data entries in the dense data array is invalid. The computer system creates an associated sparse data array that includes multiple data entries with zero values as well as data entries with non-zero values. The non-zero data entries are configured to store location information and data values for each of the invalid data entries in the dense array. The zero-value data entries are inferred from the location information of the non-zero data entries. The computer system stores the location information and data values of the non-zero data entries in the sparse data array. Those data values stored in the sparse array are proportional to the number of invalid values in the dense array.

    Abstract translation: 在一个实施例中，计算机系统访问密集数据阵列中的各种不同的数据条目，其中密集数据阵列中的那些数据条目中的至少一个无效。 计算机系统创建关联的稀疏数据阵列，其包括具有零值的多个数据条目以及具有非零值的数据条目。 非零数据条目被配置为存储密集阵列中的每个无效数据条目的位置信息和数据值。 零值数据条目是从非零数据条目的位置信息推断的。 计算机系统将非零数据条目的位置信息和数据值存储在稀疏数据阵列中。 存储在稀疏数组中的那些数据值与密集数组中无效值的数目成比例。

    Data flow network
    4.
    发明授权
    Data flow network 有权
    数据流网络

    公开(公告)号：US08407728B2

    公开(公告)日：2013-03-26

    申请号：US12131449

    申请日：2008-06-02

    Applicant: Niklas Gustafsson ,  David Callahan

    Inventor： Niklas Gustafsson ,  David Callahan

    IPC: G06F9/46 ,  G06F15/16

    CPC classification number: G06F9/544

    Abstract: A compositional model referred to as a source-target pattern for connecting processes into process networks in a general, flexible, and extensible manner is provided. The model allows common process algebra constructs to be combined with data flow networks to form process networks. Process algebraic operations may be expressed in terms of the compositional model to form data flow networks that provide fully interoperable process algebraic operations between processes.

    Abstract translation: 提供了一种被称为以一般，灵活和可扩展的方式将过程连接到进程网络的源 - 目标模式的组合模型。 该模型允许将通用过程代数结构与数据流网络组合以形成流程网络。 流程代数运算可以用组合模型来表示，以形成在进程之间提供完全可互操作的进程代数运算的数据流网络。

    Metaphysically addressed cache metadata
    5.
    发明授权
    Metaphysically addressed cache metadata 有权
    形而上学的缓存元数据

    公开(公告)号：US08370577B2

    公开(公告)日：2013-02-05

    申请号：US12493165

    申请日：2009-06-26

    Applicant: Gad Sheaffer ,  David Callahan ,  Jan Gray ,  Ali-Reza Adl-Tabatabai ,  Shlomo Raikin

    Inventor： Gad Sheaffer ,  David Callahan ,  Jan Gray ,  Ali-Reza Adl-Tabatabai ,  Shlomo Raikin

    IPC: G06F12/00

    CPC classification number: G06F17/30997 ,  G06F12/0802 ,  G06F12/109

    Abstract: Storing metadata that is disjoint from corresponding data by storing the metadata to the same address as the corresponding data but in a different address space. A metadata store instruction includes a storage address for the metadata. The storage address is the same address as that for data corresponding to the metadata, but the storage address when used for the metadata is implemented in a metadata address space while the storage address, when used for the corresponding data is implemented in a different data address space. As a result of executing the metadata store instruction, the metadata is stored at the storage address. A metadata load instruction includes the storage address for the metadata. As a result of executing the metadata load instruction, the metadata stored at the address is received. Some embodiments may further implement a metadata clear instruction which clears any entries in the metadata address space.

    Abstract translation: 通过将元数据存储到与相应数据相同的地址但在不同的地址空间中，存储与相应数据不相关的元数据。 元数据存储指令包括元数据的存储地址。 存储地址与对应于元数据的数据的地址相同，但是当用于元数据的存储地址被实现在元数据地址空间中，而当用于相应数据的存储地址被实现在不同的数据地址 空间。 作为执行元数据存储指令的结果，元数据被存储在存储地址处。 元数据加载指令包括元数据的存储地址。 作为执行元数据加载指令的结果，接收存储在地址处的元数据。 一些实施例可以进一步实现清除元数据地址空间中的任何条目的元数据清除指令。

    Medical device interface system with automatic rate threshold adjustment
    7.
    发明授权
    Medical device interface system with automatic rate threshold adjustment 有权
    医疗设备接口系统具有自动速率阈值调整功能

    公开(公告)号：US07966069B2

    公开(公告)日：2011-06-21

    申请号：US11856558

    申请日：2007-09-17

    Applicant: Les Norman Peterson ,  Paula Dieterle ,  Par Lindh ,  James Kalgren ,  James O. Gilkerson ,  Allan T. Koshiol ,  Tala L Bynum ,  David Callahan

    Inventor： Les Norman Peterson ,  Paula Dieterle ,  Par Lindh ,  James Kalgren ,  James O. Gilkerson ,  Allan T. Koshiol ,  Tala L Bynum ,  David Callahan

    IPC: A61N1/02

    CPC classification number: A61N1/37247 ,  A61N1/3993 ,  G06F19/00 ,  Y10S128/903

    Abstract: An external programming system and method for implantable medical devices (IMDs) is disclosed. The external programming system includes a communication circuit, a display device, an input device, and a processor. The communication circuit is configured to link to an IMD to transmit or monitor IMD timing parameter settings. The display device is configured to display a textual representation of an IMD timing parameter setting and a specified IMD timing parameter limit, a graphical slide control comprising a movable feature indicating the IMD timing parameter setting, a graphical slide-control limit corresponding to the specified IMD timing parameter limit, and a graphical representation of physiologic information including a portion of said graphical representation aligned with the slide control movable feature. The input device is configured to adjust the movable feature in response to user input. The processor is configured to monitor or store an IMD timing parameter setting.

    Abstract translation: 公开了用于可植入医疗装置（IMD）的外部编程系统和方法。 外部编程系统包括通信电路，显示设备，输入设备和处理器。 通信电路被配置为链接到IMD以发送或监视IMD定时参数设置。 显示装置被配置为显示IMD定时参数设置和指定的IMD定时参数限制的文本表示，包括指示IMD定时参数设置的可移动特征的图形幻灯片控制，对应于指定IMD的图形幻灯片控制限制 定时参数限制，以及包括与滑动控制可移动特征对齐的所述图形表示的一部分的生理信息的图形表示。 输入设备被配置为响应于用户输入来调整可移动特征。 处理器配置为监视或存储IMD定时参数设置。

    USING BUFFERED STORES OR MONITORING TO FILTER REDUNDANT TRANSACTIONAL ACCESSES AND MECHANISMS FOR MAPPING DATA TO BUFFERED METADATA
    8.
    发明申请
    USING BUFFERED STORES OR MONITORING TO FILTER REDUNDANT TRANSACTIONAL ACCESSES AND MECHANISMS FOR MAPPING DATA TO BUFFERED METADATA 有权
    使用缓冲存储器或监视过滤冗余交易访问和将数据映射到缓冲元数据的机制

    公开(公告)号：US20110145516A1

    公开(公告)日：2011-06-16

    申请号：US12638098

    申请日：2009-12-15

    Applicant: Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Bratin Saha ,  Jan Gray ,  David Callahan ,  Burton Smith ,  Graefe Goetz

    Inventor： Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Bratin Saha ,  Jan Gray ,  David Callahan ,  Burton Smith ,  Graefe Goetz

    IPC: G06F12/00

    CPC classification number: G06F9/522 ,  G06F8/458 ,  G06F9/52 ,  G06F11/3471 ,  G06F2201/865 ,  G06F2201/87

    Abstract: A method and apparatus for accelerating a Software Transactional Memory (STM) system is herein described. A data object and metadata for the data object may each be associated with a filter, such as a hardware monitor or ephemerally held filter information. The filter is in a first, default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access to the metadata, such as a first read, access barrier operations, such as logging of the metadata; setting a read monitor; or updating ephemeral filter information with an ephemeral/buffered store operation, are performed. Upon a subsequent/redundant access to the metadata, such as a second read, access barrier operations are elided to accelerate the subsequent access based on the filter being set to the second state to indicate a previous access occurred. Additionally, mapping of data objects to ephemeral information may be provided by software, such as through a pointer to the ephemeral information associated with the data object; an offset from a base address of the data object to the ephemeral information included associated with the data object; an index into a segment containing the ephemeral information associated with the data object; mapping the data object to the ephemeral information utilizing address arithmetic; and a hash that maps the data object to ephemeral information.

    Abstract translation: 这里描述了用于加速软件事务存储器（STM）系统的方法和装置。 数据对象和数据对象的元数据可以分别与诸如硬件监视器或者瞬时保持的过滤器信息的过滤器相关联。 过滤器处于第一个默认状态，当事务的挂起期间没有发生来自数据对象的访问，例如读取。 在遇到元数据的首次访问时，例如第一读取，访问屏障操作，诸如记录元数据; 设置一个读取监视器; 或者用临时/缓冲存储操作来更新临时过滤器信息。 在对诸如第二读取的元数据的后续/冗余访问（例如第二读取）时，消除访问屏障操作以基于被设置为第二状态的过滤器来加速后续访问，以指示先前的访问发生。 另外，数据对象到短暂信息的映射可以由软件提供，例如通过指向与数据对象相关联的短暂信息的指针; 从数据对象的基地址到包括与数据对象相关联的临时信息的偏移; 指向包含与数据对象相关联的短暂信息的段的索引; 使用地址算术将数据对象映射到临时信息; 以及将数据对象映射到临时信息的散列。

    WAIT LOSS SYNCHRONIZATION
    9.
    发明申请
    WAIT LOSS SYNCHRONIZATION 有权
    等待丢失同步

    公开(公告)号：US20100332753A1

    公开(公告)日：2010-12-30

    申请号：US12493163

    申请日：2009-06-26

    Applicant: Jan Gray ,  David Callahan ,  Burton Jordan Smith ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Bratin Saha

    Inventor： Jan Gray ,  David Callahan ,  Burton Jordan Smith ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai ,  Bratin Saha

    IPC: G06F12/02 ,  G06F1/32 ,  G06F12/08

    CPC classification number: G06F12/0831 ,  G06F1/3225

    Abstract: Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locations and a read, or write monitor on a second set of one or more different memory locations are set. A processor level instruction is executed, which causes the processor to suspend executing instructions and optionally to enter a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations. A conflicting access is detected on the first or second set of one or more memory locations or a timeout is detected. As a result, the method includes resuming execution of instructions.

    Abstract translation: 在内存访问监控丢失时同步线程。 使用处理器级指令作为处理器，读取或写入监视器的指令集体系结构的一部分而被包括，以分别从第一组一个或多个存储器位置和读取的或其他存储器位置的其他代理检测写入或读取或写入 设置在第二组一个或多个不同存储单元上的写监视器。 执行处理器级指令，这使得处理器暂停执行指令，并且可选地进入低功率模式，等待丢失第一或第二组一个或多个存储器位置的读或写监视器。 在一个或多个存储器位置的第一或第二组上检测到冲突的访问，或者检测到超时。 结果，该方法包括恢复指令的执行。

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