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    Method and system for optimizing overall throughput of a PCIe/CXL host bridge
    3.
    发明申请
    Method and system for optimizing overall throughput of a PCIe/CXL host bridge 有权

    公开(公告)号：US20250156366A1

    公开(公告)日：2025-05-15

    申请号：US18657823

    申请日：2024-05-08

    Applicant: Intel Corporation

    Inventor： Cong ZHANG ,  Tao ZHAO ,  Yi Liu ,  Jian WANG ,  Fan WANG ,  Zhonghua SUN ,  Xin ZHANG ,  Di ZHANG

    IPC: G06F13/42 ,  G06F13/40

    Abstract: A method and system for optimizing overall throughput of a Peripheral Component Interconnect Express (PCIe)/Compute Express Link (CXL) host bridge. The PCIe/CXL host bridge includes a plurality of ports, and one or more devices are connected to the ports. Credits are initially allocated to the ports of the PCIe/CXL host bridge. A link status on the ports of the PCIe/CXL host bridge and/or a status of scheduled workloads on a host are then determined. The credits allocated to the ports of the PCIe/CXL host bridge are adjusted based on the link status and/or the status of scheduled workloads. A PCIe driver may detect the link status of each port of the PCIe/CXL host bridge and request to adjust the credits based on the link status. An orchestration software that is configured to schedule and switch workloads may request to adjust the credits based on the status of scheduled workloads.

    Quantum dot devices with multiple barrier gates between adjacent plunger gates
    4.
    发明授权
    Quantum dot devices with multiple barrier gates between adjacent plunger gates 有权

    公开(公告)号：US12302763B1

    公开(公告)日：2025-05-13

    申请号：US17695717

    申请日：2022-03-15

    Applicant: Intel Corporation

    Inventor： Matthew Jon Curry ,  Hubert C. George ,  James S. Clarke

    IPC: H10N60/10 ,  G06N10/00 ,  G06N10/40 ,  H01L29/66 ,  H03K17/92 ,  H10D48/00 ,  H10N69/00

    Abstract: Quantum dot devices with multiple barrier gates between adjacent plunger gates are disclosed. Multiple barrier gates between two adjacent plunger gates are coupled to respective signal sources and may be individually controlled by signals being applied to one or more of the multiple barrier gates to control electrostatics so that the potential barrier between quantum dots formed under adjacent plunger gates may be adjusted. Appropriate signals are to be applied to two or more of the multiple barrier gates between a pair of adjacent plunger gates in order to realize sufficient coupling of quantum dots. Such quantum dot devices provide strong spatial localization of the quantum dots, good control over quantum dot interactions and manipulation, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

    Ultra-low latency medium access control design for 802.11
    6.
    发明授权
    Ultra-low latency medium access control design for 802.11 有权

    公开(公告)号：US12302428B2

    公开(公告)日：2025-05-13

    申请号：US17850781

    申请日：2022-06-27

    Applicant: Intel Corporation

    Inventor： Dave Cavalcanti ,  Juan Fang ,  Minyoung Park ,  Javier Perez-Ramirez

    IPC: H04W76/15 ,  H04W72/0446 ,  H04W88/06 ,  H04W88/10

    Abstract: This disclosure describes systems, methods, and devices related to ultra-low latency (ULL). A device may generate a first frame to be sent on a first link in a multi-link operation (MLO) with an multi-link device (MLD). The device may generate a second frame to be sent on a second link in the MLO with the MLD. The device may divide the first frame and the second frame into a first plurality of segments and a second plurality of segments separated by one or more first and second time gaps, respectively. The device may indicate to a first station device having a ULL packet to initiate a transmission of the ULL packet during an earliest time gap on the first link. The device may cause to send the one or more first and second plurality of segments on the first link and second link respectively.

    Methods and apparatus to determine a location of an audio source
    7.
    发明授权
    Methods and apparatus to determine a location of an audio source 有权

    公开(公告)号：US12302060B2

    公开(公告)日：2025-05-13

    申请号：US17359532

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Krzysztof Pawlak

    IPC: H04R3/00 ,  H04R1/40

    Abstract: Methods, apparatus, systems, and articles of manufacture to determine a physical location of an audio source are disclosed. One such apparatus includes a microphone set identifier to identify ordered microphone sets from a plurality of microphones and an estimated source location calculator to calculate estimated source locations for the audio source. The apparatus further includes an estimation error calculator to calculate respective estimation errors for corresponding ones of the estimated source locations. A likelihood calculator calculates respective likelihood values for corresponding ones of the estimated source locations and a first one of the estimated source location associated with a selected one of the likelihood values is used to represent the physical location of the audio source.

    Move stream content from point to point over the existing IP gateway
    8.
    发明授权
    Move stream content from point to point over the existing IP gateway 有权

    公开(公告)号：US12301928B2

    公开(公告)日：2025-05-13

    申请号：US18430690

    申请日：2024-02-02

    Applicant: Intel Corporation

    Inventor： Li-Gong Kao ,  Chuan Hua LEI

    IPC: H04N21/436 ,  H04N21/414 ,  H04N21/4363 ,  H04N21/61

    Abstract: An access point for a home network is provided. The access point includes a processor circuit. When executing software, the processor circuit is configured to receive media stream data from a media source external to the access point. Further, the processor circuit is configured to generate output data for a display device based on the received media stream data. The access point also includes an output interface for connecting to the display device. The output interface is configured to output the output data.

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