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    Programmable multifield parser packet
    1.
    发明授权
    Programmable multifield parser packet 失效
    可编程多字段解析器包

    公开(公告)号：US08681819B2

    公开(公告)日：2014-03-25

    申请号：US13017963

    申请日：2011-01-31

    Applicant: Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

    Inventor： Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

    IPC: G01R31/08 ,  H04J3/24

    CPC classification number: H04L69/22

    Abstract: A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.

    Abstract translation: 一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小） 由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

    Systems and methods for multi-frame control blocks
    6.
    发明申请
    Systems and methods for multi-frame control blocks 有权

    公开(公告)号：US20060206684A1

    公开(公告)日：2006-09-14

    申请号：US11076218

    申请日：2005-03-09

    Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    IPC: G06F12/00 ,  G06F9/34

    CPC classification number: H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

    Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

    Method and structure for enqueuing data packets for processing
    8.
    发明申请
    Method and structure for enqueuing data packets for processing 失效
    排队处理数据包的方法和结构

    公开(公告)号：US20060039376A1

    公开(公告)日：2006-02-23

    申请号：US10868725

    申请日：2004-06-15

    Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

    IPC: H04L12/56 ,  H04L12/28

    CPC classification number: H04L49/90 ,  H04L49/9042 ,  H04L49/9073 ,  H04L69/22

    Abstract: A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

    Abstract translation: 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。

    Method for prevention of out-of-order delivery of data
    9.
    发明申请
    Method for prevention of out-of-order delivery of data 失效
    防止数据乱序传送的方法

    公开(公告)号：US20050259659A1

    公开(公告)日：2005-11-24

    申请号：US10850296

    申请日：2004-05-20

    Applicant: Claude Basso ,  Jean Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    Inventor： Claude Basso ,  Jean Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    IPC: H04L12/56 ,  H04L29/06

    CPC classification number: H04L69/166 ,  H04L29/06 ,  H04L69/16

    Abstract: A method for sequencing delivery of information packets from a router having several processing elements to a receiving processing installation, wherein delivery of the packets must be completed in the order the packets arrive at the router. A linked list of packets is formed in the order they are received at the router, and each packet fragmented into successive fragments. Each fragment is processed at the router. The last fragment of each packet in each linked list is labeled with the sequence in which the packet was received, and enqueued in the order labeled for each last fragment on each linked list. Each fragment of each packet is delivered as processed, except the last fragment of each packet on its linked list to the receiving processor installation, and thereafter, transmitting the final fragment of each packet after processing only if that fragment is at the head of the queue.

    Abstract translation: 一种用于将信息分组从具有多个处理元件的路由器传送到接收处理设备的方法，其中分组的传送必须按分组到达路由器的顺序完成。 分组的链表以它们在路由器处接收的顺序形成，并且每个分组被分段成连续的片段。 每个片段在路由器处理。 每个链表中每个数据包的最后一个片段都标有接收数据包的顺序，并按照每个链表上每个最后一个片段标记的顺序排队。 每个分组的每个片段被处理，除了其链接列表上的每个分组的最后片段到接收处理器安装，然后在处理之后仅在该片段位于队列的头部时发送每个分组的最后片段 。

    Data communications
    10.
    发明授权
    Data communications 失效
    数据通信

    公开(公告)号：US6144637A

    公开(公告)日：2000-11-07

    申请号：US991911

    申请日：1997-12-16

    Applicant: Jean Calvignac ,  Fabrice Verplanken ,  Daniel Orsatti

    Inventor： Jean Calvignac ,  Fabrice Verplanken ,  Daniel Orsatti

    IPC: H04L12/70 ,  H04Q11/04 ,  H04J3/14

    CPC classification number: H04Q11/0478 ,  H04L2012/568

    Abstract: Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.

    Abstract translation: 描述了用于分组数据通信网络（诸如异步传输模式（ATM））网络的流量整形装置。 该装置包括用于具有多个不同期望分组传输速率的业务的一个或多个分组队列，每个队列被分配给具有预定的期望分组传送速率的连接。 每个传入的数据包被引导到适当的队列。 多个定时电路中的每一个在一系列频率中以不同的频率工作。 选择频率使得可以通过对来自多于一个定时电路的输出求和来建立连接的期望分组传送速率。

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