公开(公告)号：US20170230037A1

公开(公告)日：2017-08-10

申请号：US15496924

申请日：2017-04-25

Applicant: KISKEYA MICROSYSTEMS LLC

Inventor： Marc Péralte Dandin

IPC: H03K5/134 ,  H03K17/74 ,  H01L31/107 ,  H01L31/02 ,  H03H11/26

CPC classification number: H03K5/134 ,  G01J1/44 ,  G01J2001/442 ,  G01J2001/4466 ,  H01L31/02027 ,  H01L31/107 ,  H03H11/265 ,  H03K5/133 ,  H03K5/1534 ,  H03K17/74 ,  H03K2005/00026 ,  H03K2005/00156

Abstract: A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

公开(公告)号：US10594306B2

公开(公告)日：2020-03-17

申请号：US15496924

申请日：2017-04-25

Applicant: KISKEYA MICROSYSTEMS LLC

Inventor： Marc Péralte Dandin

IPC: H03K5/134 ,  H01L31/02 ,  H01L31/107 ,  H03H11/26 ,  H03K17/74 ,  G01J1/44 ,  H03K5/1534 ,  H03K5/00 ,  H03K5/133

Abstract: A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

公开(公告)号：US09671284B1

公开(公告)日：2017-06-06

申请号：US15407683

申请日：2017-01-17

Applicant: KISKEYA MICROSYSTEMS LLC

Inventor： Marc Péralte Dandin

IPC: G01J1/44 ,  H03K5/1534 ,  H03K5/00

CPC classification number: G01J1/44 ,  G01J2001/442 ,  G01J2001/4466 ,  H01L31/02027 ,  H03K5/134 ,  H03K5/1534 ,  H03K2005/00026 ,  H03K2005/00156

Abstract: A circuit is provided. The circuit includes a single-photon avalanche diode. The circuit further includes a delay element comprising a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay element. The delay element is configured to receive, at an inverting section, an event signal indicative of an avalanche event in the single-photon avalanche diode. Furthermore, the delay element is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge of the event signal being actively delayed by the delay element when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.