公开(公告)号：US20130032955A1

公开(公告)日：2013-02-07

申请号：US13204507

申请日：2011-08-05

Applicant: Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

Inventor： Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/31 ,  H01L23/29 ,  H01L21/28

CPC classification number: H01L21/76879 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/31 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

公开(公告)号：US08258629B2

公开(公告)日：2012-09-04

申请号：US12060999

申请日：2008-04-02

Applicant: Joung-Wei Liou ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Joung-Wei Liou ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L23/48

CPC classification number: H01L23/522 ,  H01L21/02348 ,  H01L21/31 ,  H01L21/76825 ,  H01L23/53295 ,  H01L23/562 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05553 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.

Abstract translation: 提供了包括反射金属焊盘的集成电路结构。 集成电路结构包括半导体衬底; 覆盖半导体衬底的第一低k电介质层，其中第一低k电介质层是顶部低k电介质层; 位于第一低k电介质层下面的第二低k电介质层; 以及第二低k电介质层中的反射金属焊盘。

公开(公告)号：US20110207329A1

公开(公告)日：2011-08-25

申请号：US12712515

申请日：2010-02-25

Applicant: Po-Cheng SHIH ,  Kuan-Chen WANG ,  Chung-Chi KO ,  Keng-Chu LIN ,  Tai-Yen PENG ,  Wen-Kuo HSIEH ,  Chih-Hao CHEN

Inventor： Po-Cheng SHIH ,  Kuan-Chen WANG ,  Chung-Chi KO ,  Keng-Chu LIN ,  Tai-Yen PENG ,  Wen-Kuo HSIEH ,  Chih-Hao CHEN

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813

Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.

Abstract translation: 光刻图案的方法包括在材料层上形成掩模层并在掩模层上形成覆盖层。 覆盖层是对材料层的图案化处理的蚀刻反应性更高的含硼层。 通过使含硼层适合作为覆盖层，可以减小掩模层的厚度。 因此，也可以实现用于在材料层中形成互连金属化的更好的间隙填充。

公开(公告)号：USRE42514E1

公开(公告)日：2011-07-05

申请号：US12943479

申请日：2010-11-10

Applicant: Fang-Wen Tsai ,  Kuan-Chen Wang ,  Keng-Chu Lin ,  Chih-Lung Lin ,  Shwang-Ming Jeng

Inventor： Fang-Wen Tsai ,  Kuan-Chen Wang ,  Keng-Chu Lin ,  Chih-Lung Lin ,  Shwang-Ming Jeng

IPC: H01L23/58 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.

Abstract translation: 用于高级互连的极低k（ELK）电介质膜方案包括上ELK电介质层和具有不同折射率的下ELK电介质。 上部ELK介电层的折射率大于下部ELK介电层的折射率。

公开(公告)号：USRE41935E1

公开(公告)日：2010-11-16

申请号：US11655743

申请日：2007-01-19

Applicant: Shing-Chyang Pan ,  Keng-Chu Lin ,  Wen-Chih Chiou ,  Shwang-Ming Jeng

Inventor： Shing-Chyang Pan ,  Keng-Chu Lin ,  Wen-Chih Chiou ,  Shwang-Ming Jeng

IPC: H01L21/26 ,  H01L21/324 ,  H01L21/42 ,  H01L21/4763 ,  H01L21/477

CPC classification number: H01L21/76814 ,  H01L21/3003 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/76807 ,  H01L21/76843

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

Abstract translation: 一种用于等离子体处理各向异性蚀刻的开口以改善裂纹起始和传播阻力的方法，包括提供具有包括各向异性蚀刻的开口的半导体晶片，所述工艺表面包括至少部分延伸穿过介电绝缘层的工艺表面; 在至少一个等离子体处理等离子体处理包括各向异性蚀刻的开口的工艺表面，以改善随后沉积的难熔金属粘合/阻挡层在其上的粘附; 并且毯子沉积至少一个难熔金属粘合/阻挡层以对各向异性蚀刻的开口进行排列。

公开(公告)号：US20090250792A1

公开(公告)日：2009-10-08

申请号：US12060999

申请日：2008-04-02

Applicant: Joung-Wei Liou ,  Keng-Chu Lin ,  Shwang-Ming Jeng

Inventor： Joung-Wei Liou ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC: H01L23/544

CPC classification number: H01L23/522 ,  H01L21/02348 ,  H01L21/31 ,  H01L21/76825 ,  H01L23/53295 ,  H01L23/562 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05553 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.

Abstract translation: 提供了包括反射金属焊盘的集成电路结构。 集成电路结构包括半导体衬底; 覆盖半导体衬底的第一低k电介质层，其中第一低k电介质层是顶部低k电介质层; 位于第一低k电介质层下面的第二低k电介质层; 以及第二低k电介质层中的反射金属焊盘。

公开(公告)号：US07466027B2

公开(公告)日：2008-12-16

申请号：US11531304

申请日：2006-09-13

Applicant: Chung-Chi Ko ,  Keng-Chu Lin ,  Chia-Cheng Chou

Inventor： Chung-Chi Ko ,  Keng-Chu Lin ,  Chia-Cheng Chou

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/02203 ,  H01L21/3121 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and the via opening exposes a portion of the substrate. A liner layer is formed on sidewalls of the low-k dielectric layer exposed by the trench and via protions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via protions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials. A conformal conductive barrier layer is formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate. A conductive layer is formed on the conductive barrier layer, filling in the trench and via openings.

Abstract translation: 提供互连结构。 互连结构的示例性实施例包括其上具有低k电介质层的衬底。 通孔开口和沟槽开口形成在低k电介质层中，其中沟槽开口形成在通孔开口上方，通孔开口暴露出衬底的一部分。 衬底层形成在由槽沟露出的低k电介质层的侧壁上，并且通过沟槽和由沟槽通孔部分露出的底表面，其中低k电介质层的侧壁上的衬垫层的部分暴露于 形成在由沟槽部分露出的底表面上的沟槽和通孔保护层以及衬垫层的部分包括不同的材料。 在沟槽和通孔开口中形成共形导电阻挡层，覆盖衬垫层和衬底的暴露部分。 在导电阻挡层上形成导电层，填充沟槽和通孔。

公开(公告)号：US20070243720A1

公开(公告)日：2007-10-18

申请号：US11404020

申请日：2006-04-14

Applicant: Chung-Chi Ko ,  Keng-Chu Lin ,  Tien-I Bao

Inventor： Chung-Chi Ko ,  Keng-Chu Lin ,  Tien-I Bao

IPC: H01L21/31

CPC classification number: H01L21/3105 ,  H01L21/31058 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825

Abstract: An UV treatment for making a low-k dielectric layer having improved properties in a damascene structure. A low-k dielectric layer in a damascene structure is subjected to an UV treatment with He gas or H2 gas to eliminate etching damage to the exposed surfaces of the low-k dielectric layer.

Abstract translation: 用于制造具有改进的镶嵌结构性能的低k电介质层的UV处理。 用Ho气体或H 2 O 2气体对镶嵌结构中的低k电介质层进行UV处理，以消除对低k电介质层的暴露表面的蚀刻损伤。

公开(公告)号：US20070202676A1

公开(公告)日：2007-08-30

申请号：US11361331

申请日：2006-02-24

Applicant: Ming Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

Inventor： Ming Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC: H01L21/44

CPC classification number: H01L21/76834 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846

Abstract: A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.

Abstract translation: 提供了一种形成在多孔电介质层中的开口的半导体结构。 沿着开口的侧壁的电介质层的暴露的孔被密封。 密封可以包括选择性或非选择性沉积方法。 密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。 如其制造方法那样提供具有孔密封层的镶嵌互连结构。

公开(公告)号：US07230596B2

公开(公告)日：2007-06-12

申请号：US11061333

申请日：2005-02-18

Applicant: Hong-Ru Guo ,  Keng-Chu Lin ,  Chen-Chung Yang

Inventor： Hong-Ru Guo ,  Keng-Chu Lin ,  Chen-Chung Yang

IPC: G09G3/30

CPC classification number: G09G3/3233 ,  G09G2300/0809 ,  G09G2320/0233 ,  G09G2320/029 ,  G09G2320/041

Abstract: An active organic electroluminescence display panel module comprising a substrate, a plurality of organic light-emitting devices, a light-emitting device driving unit and a temperature sensor unit are provided. The light-emitting device driving unit is electrically connected to the organic light-emitting devices for driving them. The temperature sensor unit is disposed on the substrate for sensing the temperature of the active organic electroluminescence display panel. The temperature sensor unit is also electrically connected to the light-emitting device driving unit for providing a signal to the light-emitting device driving unit in response to the sensed temperature. Accordingly, the light-emitting device driving unit can adjust the driving voltage of the organic light-emitting devices in the active organic electroluminescence display panel to reduce overall power consumption and provide an accurate grayscale to improve the quality of displayed images.

Abstract translation: 提供一种有源电致发光显示面板模块，其包括基板，多个有机发光器件，发光器件驱动单元和温度传感器单元。 发光器件驱动单元电连接到用于驱动它们的有机发光器件。 温度传感器单元设置在用于感测活性有机电致发光显示面板的温度的基板上。 温度传感器单元还电连接到发光器件驱动单元，用于响应于感测到的温度向发光器件驱动单元提供信号。 因此，发光器件驱动单元可以调节活性有机电致发光显示面板中的有机发光器件的驱动电压，以降低整体功耗，并提供准确的灰度级以提高显示图像的质量。