公开(公告)号：US09048186B2

公开(公告)日：2015-06-02

申请号：US12879371

申请日：2010-09-10

Applicant: Kuo Bin Huang ,  Hsin-Chien Lu ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Kuo Bin Huang ,  Hsin-Chien Lu ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/28238 ,  H01L21/02071 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.

Abstract translation: 提供一种用于形成集成电路的方法。 该方法包括在衬底上形成栅极电介质结构。 形成与该栅电介质结构接触的含钛牺牲层。 基本上除去了整个含钛牺牲层。

公开(公告)号：US20120086075A1

公开(公告)日：2012-04-12

申请号：US13327992

申请日：2011-12-16

Applicant: Kuo Bin HUANG ,  Ssu-Yi LI ,  Ryan Chia-Jen CHEN ,  Chi-Ming YANG ,  Chyi Shyuan CHERN ,  Chin-Hsiang LIN

Inventor： Kuo Bin HUANG ,  Ssu-Yi LI ,  Ryan Chia-Jen CHEN ,  Chi-Ming YANG ,  Chyi Shyuan CHERN ,  Chin-Hsiang LIN

IPC: H01L27/088

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.

Abstract translation: 具有金属栅极结构的半导体结构包括具有第一栅极的第一型场效应晶体管，包括：基板上的高k电介质材料，高k电介质材料层上的第一金属层，具有第一功函数，以及 在第一金属层上的第一铝层。 第一铝层包括包含铝，氮和氧的界面层。 该器件还包括具有第二栅极的第二类场效应晶体管，其包括：衬底上的高k电介质材料，高k电介质材料层上的第二金属层，具有不同于第一功函数的第二功函数， 和在第二金属层上的第二铝层。

公开(公告)号：US20130143406A1

公开(公告)日：2013-06-06

申请号：US13311948

申请日：2011-12-06

Applicant: Yu-Rung Hsu ,  Sung-Hsun Wu ,  Kuo Bin Huang

Inventor： Yu-Rung Hsu ,  Sung-Hsun Wu ,  Kuo Bin Huang

IPC: H01L21/311

CPC classification number: G03F7/42 ,  G03F7/423 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/67115

Abstract: A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成图案化的光致抗蚀剂层，对图案化的光致抗蚀剂层执行等离子体灰化处理，从而去除图案化光致抗蚀剂层的一部分，将图案化的光致抗蚀剂层暴露于宽带紫外线辐射和臭氧， 从而去除图案化光致抗蚀剂层的其它部分，并且在将图案化的光致抗蚀剂层暴露于宽带紫外线辐射和臭氧之后，对图案化的光致抗蚀剂层进行清洁。

公开(公告)号：US08357617B2

公开(公告)日：2013-01-22

申请号：US12371672

申请日：2009-02-16

Applicant: Matt Yeh ,  Shun Wu Lin ,  Chi-Chun Chen ,  Ryan Chia-Jen Chen ,  Yi-Hsing Chen ,  Chien-Hao Chen ,  Donald Y. Chao ,  Kuo-Bin Huang

Inventor： Matt Yeh ,  Shun Wu Lin ,  Chi-Chun Chen ,  Ryan Chia-Jen Chen ,  Yi-Hsing Chen ,  Chien-Hao Chen ,  Donald Y. Chao ,  Kuo-Bin Huang

IPC: H01L21/302

CPC classification number: H01L21/28105 ,  H01L21/28123 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/401

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

公开(公告)号：US06642128B1

公开(公告)日：2003-11-04

申请号：US10140396

申请日：2002-05-06

Applicant: Ching-Shan Lu ,  Kuo-Bin Huang ,  Jih-Churng Twu

Inventor： Ching-Shan Lu ,  Kuo-Bin Huang ,  Jih-Churng Twu

IPC: H01L21322

CPC classification number: H01L21/76224

Abstract: A method for preventing oxide layer peeling in a high temperature annealing process including providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.

Abstract translation: 一种用于防止在高温退火过程中氧化层剥离的方法，包括提供多个间隔堆叠的半导体晶片，用于执行包括环境氮气的高温退火工艺，所述多个间隔堆叠的半导体晶片被堆叠，使得处理表面包括 在进行高温退火处理之前，至少一个半导体晶片的氧化物层与另一半导体晶片的背面相邻，所述背面具有形成在其上的氮化硅层; 并进行高温退火处理。

公开(公告)号：US08734662B2

公开(公告)日：2014-05-27

申请号：US13311948

申请日：2011-12-06

Applicant: Yu-Rung Hsu ,  Sung Hsun Wu ,  Kuo Bin Huang

Inventor： Yu-Rung Hsu ,  Sung Hsun Wu ,  Kuo Bin Huang

IPC: B44C1/22

CPC classification number: G03F7/42 ,  G03F7/423 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/67115

Abstract: A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成图案化的光致抗蚀剂层，对图案化的光致抗蚀剂层执行等离子体灰化处理，从而去除图案化光致抗蚀剂层的一部分，将图案化的光致抗蚀剂层暴露于宽带紫外线辐射和臭氧， 从而去除图案化光致抗蚀剂层的其它部分，并且在将图案化的光致抗蚀剂层暴露于宽带紫外线辐射和臭氧之后，对图案化的光致抗蚀剂层进行清洁。

公开(公告)号：US20130078809A1

公开(公告)日：2013-03-28

申请号：US13244337

申请日：2011-09-24

Applicant: Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L21/306

CPC classification number: H01L21/6708 ,  H01L21/31111

Abstract: A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

Abstract translation: 公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。 在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热到第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。

公开(公告)号：US08237231B2

公开(公告)日：2012-08-07

申请号：US13327992

申请日：2011-12-16

Applicant: Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L27/088

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.

Abstract translation: 具有金属栅极结构的半导体结构包括具有第一栅极的第一型场效应晶体管，包括：基板上的高k电介质材料，高k电介质材料层上的第一金属层，具有第一功函数，以及 在第一金属层上的第一铝层。 第一铝层包括包含铝，氮和氧的界面层。 该器件还包括具有第二栅极的第二类场效应晶体管，其包括：衬底上的高k电介质材料，高k电介质材料层上的第二金属层，具有不同于第一功函数的第二功函数， 和在第二金属层上的第二铝层。

公开(公告)号：US08119473B2

公开(公告)日：2012-02-21

申请号：US12651017

申请日：2009-12-31

Applicant: Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/8232

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench.

Abstract translation: 本公开还提供了制造金属栅极叠层的方法的另一个实施例。 该方法包括在衬底上形成第一虚拟栅极和第二虚拟栅极; 从第一伪栅极去除多晶硅层，产生第一栅极沟槽; 在所述第一栅极沟槽中形成第一金属层和第一铝层; 对基材进行化学机械抛光（CMP）工艺; 使用含氮和氧的气体对所述第一铝层进行退火处理，在所述第一铝层上形成铝，氮和氧的界面层; 然后从第二伪栅极去除多晶硅层，产生第二栅极沟槽; 以及在所述第二栅极沟槽中的所述第二金属层上形成第二金属层和第二铝层。

公开(公告)号：US20110156166A1

公开(公告)日：2011-06-30

申请号：US12651017

申请日：2009-12-31

Applicant: Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench.

Abstract translation: 本公开还提供了制造金属栅极叠层的方法的另一个实施例。 该方法包括在衬底上形成第一虚拟栅极和第二虚拟栅极; 从第一伪栅极去除多晶硅层，产生第一栅极沟槽; 在所述第一栅极沟槽中形成第一金属层和第一铝层; 对基材进行化学机械抛光（CMP）工艺; 使用含氮和氧的气体对所述第一铝层进行退火处理，在所述第一铝层上形成铝，氮和氧的界面层; 然后从第二虚拟栅极去除多晶硅层，产生第二栅极沟槽; 以及在所述第二栅极沟槽中的所述第二金属层上形成第二金属层和第二铝层。