公开(公告)号：US08987086B2

公开(公告)日：2015-03-24

申请号：US13555831

申请日：2012-07-23

Applicant: Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

Inventor： Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

IPC: H01L29/94 ,  H01L27/08 ,  H01L27/06 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

公开(公告)号：US20100213572A1

公开(公告)日：2010-08-26

申请号：US12618021

申请日：2009-11-13

Applicant: Kuo-Cheng Ching ,  Kuo-Chi Tu

Inventor： Kuo-Cheng Ching ,  Kuo-Chi Tu

IPC: H01L29/92

CPC classification number: H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively.

Abstract translation: 集成电路结构包括具有第一区域和第二区域的芯片。 在第一区域形成第一金属绝缘体金属（MIM）电容器。 第一MIM电容器具有第一底部电极; 位于所述第一底部电极之上的第一顶部电极; 以及在所述第一底部电极和所述第一顶部电极之间并邻接所述第一电极绝缘体。 第二MIM电容器在第二区域中，并且与第一MIM电容器基本一致。 第二MIM电容器包括第二底部电极; 在所述第二底部电极上方的第二顶部电极; 以及在所述第二底部电极和所述第二顶部电极之间并邻接所述第二电极绝缘体。 第二电容绝缘体与第一电容绝缘体不同。 第一顶部电极和第一底部电极可以分别与第二顶部电极和第二底部电极同时形成。

公开(公告)号：US09006829B2

公开(公告)日：2015-04-14

申请号：US13594190

申请日：2012-08-24

Applicant: Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Zhiqiang Wu

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/165 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.

Abstract translation: 其中，提供了包括对准的栅极的半导体器件和用于形成半导体器件的方法。 半导体器件包括根据多门结构形成的栅极，例如栅极全绕结构。 栅极的第一栅极部分形成在半导体器件的第一沟道上方。 栅极的第二栅极部分形成在第一沟道下方，并与第一栅极部分对准。 在形成栅极的实例中，在形成于衬底上的半导体层内蚀刻空腔。 围绕至少一些空腔形成电介质层以限定空腔的区域，第二栅极部分将以其与第一栅极部分的自对准方式形成。 以这种方式，半导体器件包括与第二栅极部分对准的第一栅极部分。

公开(公告)号：US08680576B2

公开(公告)日：2014-03-25

申请号：US13473149

申请日：2012-05-16

Applicant: Kuo-Cheng Ching ,  Shi Ning Ju ,  Cary Chia-Chiung Lo ,  Huicheng Chang ,  Chun Chung Su

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Cary Chia-Chiung Lo ,  Huicheng Chang ,  Chun Chung Su

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Abstract translation: 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括第一区域和第二区域的衬底。 半导体器件还包括形成在衬底上并且在第一区域中的第一和第二隔离区域之间的第一缓冲层，以及形成在衬底上以及第二区域中的第一和第二隔离区域之间的第二缓冲层。 半导体器件还包括形成在第一缓冲层之上且在第一区域中的第一和第二隔离区之间的第一鳍结构，以及形成在第二缓冲层之上以及在第二区中的第一和第二隔离区之间的第二鳍结构 。 第一缓冲层包括与第二缓冲层的顶表面不同的顶表面。

公开(公告)号：US08436408B2

公开(公告)日：2013-05-07

申请号：US12212096

申请日：2008-09-17

Applicant: Kuo-Chi Tu ,  Huey-Chi Chu ,  Kuo-Cheng Ching

Inventor： Kuo-Chi Tu ,  Huey-Chi Chu ,  Kuo-Cheng Ching

IPC: H01L27/108

CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.

Abstract translation: 集成电路包括具有耦合在一对电源节点之间的多个有源元件的电路模块和耦合到电路模块的电容去耦模块。 电容去耦模块包括串联耦合在一对电源节点之间的多个金属 - 绝缘体 - 金属（MiM）电容器，其中供电节点之间的电压在多个MiM电容器之间分开，从而减小电容器上的电压应力 。

公开(公告)号：US20100224925A1

公开(公告)日：2010-09-09

申请号：US12397948

申请日：2009-03-04

Applicant: Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

Inventor： Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

IPC: H01L27/108 ,  H01L29/92 ,  H01L21/02

CPC classification number: H01L27/0805 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

公开(公告)号：US20100065944A1

公开(公告)日：2010-03-18

申请号：US12212096

申请日：2008-09-17

Applicant: Kuo-Chi TU ,  Huey-Chi Chu ,  Kuo-Cheng Ching

Inventor： Kuo-Chi TU ,  Huey-Chi Chu ,  Kuo-Cheng Ching

IPC: H01L29/92

CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.

Abstract translation: 集成电路包括具有耦合在一对电源节点之间的多个有源元件的电路模块和耦合到电路模块的电容去耦模块。 电容去耦模块包括串联耦合在一对电源节点之间的多个金属 - 绝缘体 - 金属（MiM）电容器，其中供电节点之间的电压在多个MiM电容器之间分开，从而减小电容器上的电压应力 。

公开(公告)号：US20130307021A1

公开(公告)日：2013-11-21

申请号：US13473149

申请日：2012-05-16

Applicant: Kuo-Cheng Ching ,  Shi Ning Ju ,  Cary Chia-Chiung Lo ,  Huicheng Chang ,  Chun Chung Su

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Cary Chia-Chiung Lo ,  Huicheng Chang ,  Chun Chung Su

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.

Abstract translation: 公开了半导体器件和半导体器件的制造方法。 示例性的半导体器件包括包括第一区域和第二区域的衬底。 半导体器件还包括形成在衬底上并且在第一区域中的第一和第二隔离区域之间的第一缓冲层，以及形成在衬底上以及第二区域中的第一和第二隔离区域之间的第二缓冲层。 半导体器件还包括形成在第一缓冲层之上且在第一区域中的第一和第二隔离区之间的第一鳍结构，以及形成在第二缓冲层之上以及在第二区中的第一和第二隔离区之间的第二鳍结构 。 第一缓冲层包括与第二缓冲层的顶表面不同的顶表面。

公开(公告)号：US20120289021A1

公开(公告)日：2012-11-15

申请号：US13555831

申请日：2012-07-23

Applicant: Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

Inventor： Kuo-Cheng Ching ,  Kuo-Chi Tu ,  Chun-Yao Chen

IPC: H01L21/02

CPC classification number: H01L27/0805 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

公开(公告)号：US08143699B2

公开(公告)日：2012-03-27

申请号：US12618021

申请日：2009-11-13

Applicant: Kuo-Cheng Ching ,  Kuo-Chi Tu

Inventor： Kuo-Cheng Ching ,  Kuo-Chi Tu

IPC: H01L29/92

CPC classification number: H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively.

Abstract translation: 集成电路结构包括具有第一区域和第二区域的芯片。 在第一区域形成第一金属绝缘体金属（MIM）电容器。 第一MIM电容器具有第一底部电极; 位于所述第一底部电极之上的第一顶部电极; 以及在所述第一底部电极和所述第一顶部电极之间并邻接所述第一电极绝缘体。 第二MIM电容器在第二区域中，并且与第一MIM电容器基本一致。 第二MIM电容器包括第二底部电极; 在所述第二底部电极上方的第二顶部电极; 以及在所述第二底部电极和所述第二顶部电极之间并邻接所述第二电极绝缘体。 第二电容绝缘体与第一电容绝缘体不同。 第一顶部电极和第一底部电极可以分别与第二顶部电极和第二底部电极同时形成。