-
公开(公告)号：US20060072261A1
公开(公告)日：2006-04-06
申请号：US11234999
申请日：2005-09-26
Applicant: Reinhold Bayerer , Markus Thoben
Inventor： Reinhold Bayerer , Markus Thoben
IPC: H02H9/00
CPC classification number: H01L23/5385 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/48227 , H01L2224/49111 , H01L2924/00014 , H01L2924/0102 , H01L2924/01068 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A power semiconductor module (1) has power semiconductor components (2, 4, 6, 8, 10, 12) arranged on a substrate (14), at least one portion of which components is connected in parallel and arranged symmetrically on the substrate (14). A second conduction plane (24, 26) is provided for making contact with the power semiconductor components (2, 4, 6, 8, 10, 12). The second conduction plane is arranged in a manner electrically insulated from the substrate surface (16) above the surfaces of the power semiconductor components (2, 4, 6, 8, 10, 12) that are remote from the substrate surface (16).
Abstract translation: 功率半导体模块（1）具有布置在基板（14）上的功率半导体部件（2,4,6,8,10,12），其中至少一部分部件并联连接并对称地布置在基板上 14）。 提供第二导电平面（24,26）以与功率半导体部件（2,4,6,8,10,12）接触。 第二导电平面以远离基板表面（16）的功率半导体部件（2,4,6,8,10,12）的表面之上与基板表面（16）电绝缘的方式布置。
-
公开(公告)号：US06936982B2
公开(公告)日：2005-08-30
申请号：US10701079
申请日：2003-11-05
Applicant: Stefan Diesner , Mirko Horaschek , Juergen Huertgen , Werner Kopmeier , Lorenz Slansky , Markus Thoben
Inventor： Stefan Diesner , Mirko Horaschek , Juergen Huertgen , Werner Kopmeier , Lorenz Slansky , Markus Thoben
Abstract: Device for actuating a plurality of actuators (1) in a transportation device, which has a plurality of output stages (2, 3, 4, 5) and a control circuit for actuating the output stages (2, 3, 4, 5), the output stages (2, 3, 4, 5) each connecting through the current in order to activate the actuators (1) and each output stage (2, 3, 4, 5) being connected in electrically conductive fashion to an actuator (1, 9). A plurality of output stages (2, 3, 4, 5) is additionally connected to in each case, one further actuator (1, 9) by the control circuit. The control circuit is actuated in such a way that an output stage (2, 3, 4, 5) can actuate either the first or the further actuator (1, 9) with the output stages (2, 3, 4, 5) being interconnected to one another and/or to the actuators (1, 9) in the manner of a matrix so that a plurality of row lines (6) and a plurality of column lines (7), at whose points of intersection (8) the actuators (1) are arranged, are provided.
Abstract translation: 用于在具有多个输出级（2,3,4,5）和用于致动输出级（2,3,4,5）的控制电路的运输装置中致动多个致动器（1）的装置， 每个通过电流连接以便激活致动器（1）的输出级（2,3,4,5）和以导电方式连接到致动器（1）的每个输出级（2,3,4,5） ，9）。 在每种情况下，多个输出级（2,3,4,5）通过控制电路另外连接一个致动器（1,9）。 控制电路被致动，使得输出级（2,3,4,5）可以通过输出级（2,3,4,5）来驱动第一或另外的致动器（1,9），其中输出级 以矩阵的方式彼此互连和/或到致动器（1,9），使得在其交点（8）处的多条行线（6）和多条列线（7） 提供了执行器（1）。
-
公开(公告)号：US20090085189A1
公开(公告)日：2009-04-02
申请号：US11866055
申请日：2007-10-02
Applicant: Markus Thoben , Richard Boettcher , Marc Buschkuehle , Hartwig Rueckert
Inventor： Markus Thoben , Richard Boettcher , Marc Buschkuehle , Hartwig Rueckert
CPC classification number: H01L23/49811 , H01L25/072 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
Abstract: One embodiment provides a semiconductor module with an electrically insulating substrate. A conductor track is arranged on the substrate. A semiconductor chip and sleeve member are arranged on the substrate and electrically connected to the conductor track. The sleeve member includes a rim with a maximum inner diameter. The module further includes a contact element. The contact element includes a first end arranged within and electrically connected to the sleeve member, a second end providing an external contact of the module, and a section arranged between the first end and the second end. The section includes a maximum outer diameter that is larger than the maximum inner diameter of the rim. The contact element is in mechanical contact with the sleeve member such that the section between both ends of the contact element is arranged outside the sleeve member and borne on the rim of the sleeve member.
Abstract translation: 一个实施例提供具有电绝缘基板的半导体模块。 导体轨道布置在基板上。 半导体芯片和套筒构件布置在基板上并电连接到导体轨道。 套筒构件包括具有最大内径的边缘。 该模块还包括接触元件。 接触元件包括布置在套筒构件内并电连接到套筒构件的第一端，提供模块的外部接触的第二端和布置在第一端和第二端之间的部分。 该部分包括大于轮辋的最大内径的最大外径。 接触元件与套筒构件机械接触，使得接触元件的两端之间的部分布置在套筒构件外部并承载在套筒构件的边缘上。
-
公开(公告)号：US20090016088A1
公开(公告)日：2009-01-15
申请号：US11816340
申请日：2006-01-19
Applicant: Reinhold Bayerer , Markus Thoben
Inventor： Reinhold Bayerer , Markus Thoben
CPC classification number: H01L24/73 , H01L24/24 , H01L24/36 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/82 , H01L25/072 , H01L2224/2402 , H01L2224/24051 , H01L2224/24226 , H01L2224/40137 , H01L2224/48091 , H01L2224/48472 , H01L2224/49111 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8384 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
Abstract: A semiconductor assembly is disclosed. One embodiment provides a first semiconductor and a second semiconductor, each having a first main connection and a second main connection arranged on opposite sides, and a carrier having a patterned metallization with a first section spaced apart from a second section. The first semiconductor is electrically connected to the first section by its second main connection, and the second semiconductor electrically connected to the second section by its second main connection. The first semiconductor chip first main connection and the second semiconductor chip first main connection are electrically connected to one another and for the connection of an external load or of an external supply voltage.
Abstract translation: 公开了半导体组件。 一个实施例提供了第一半导体和第二半导体，每个具有布置在相对侧上的第一主连接和第二主连接，以及具有图案化金属化的载体，其具有与第二部分间隔开的第一部分。 第一半导体通过其第二主连接电连接到第一部分，并且第二半导体通过其第二主连接电连接到第二部分。 第一半导体芯片第一主连接和第二半导体芯片第一主连接彼此电连接并且用于连接外部负载或外部电源电压。
-
公开(公告)号：US08472949B2
公开(公告)日：2013-06-25
申请号：US11816340
申请日：2006-01-19
Applicant: Reinhold Bayerer , Markus Thoben
Inventor： Reinhold Bayerer , Markus Thoben
IPC: H04W4/00
CPC classification number: H01L24/73 , H01L24/24 , H01L24/36 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/82 , H01L25/072 , H01L2224/2402 , H01L2224/24051 , H01L2224/24226 , H01L2224/40137 , H01L2224/48091 , H01L2224/48472 , H01L2224/49111 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8384 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
Abstract: A semiconductor assembly is disclosed. One embodiment provides a first semiconductor and a second semiconductor, each having a first main connection and a second main connection arranged on opposite sides, and a carrier having a patterned metallization with a first section spaced apart from a second section. The first semiconductor is electrically connected to the first section by its second main connection, and the second semiconductor electrically connected to the second section by its second main connection. The first semiconductor chip first main connection and the second semiconductor chip first main connection are electrically connected to one another and for the connection of an external load or of an external supply voltage.
Abstract translation: 公开了半导体组件。 一个实施例提供了第一半导体和第二半导体，每个具有布置在相对侧上的第一主连接和第二主连接，以及具有图案化金属化的载体，其具有与第二部分间隔开的第一部分。 第一半导体通过其第二主连接电连接到第一部分，并且第二半导体通过其第二主连接电连接到第二部分。 第一半导体芯片第一主连接和第二半导体芯片第一主连接彼此电连接并且用于连接外部负载或外部电源电压。
-
Patent Agency Ranking
公开(公告)号：US07816781B2
公开(公告)日：2010-10-19
申请号：US11866055
申请日：2007-10-02
Applicant: Markus Thoben , Richard Boettcher , Marc Buschkuehle , Hartwig Rueckert
Inventor： Markus Thoben , Richard Boettcher , Marc Buschkuehle , Hartwig Rueckert
IPC: H01L23/48
CPC classification number: H01L23/49811 , H01L25/072 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
Abstract: One embodiment provides a semiconductor module with an electrically insulating substrate. A conductor track is arranged on the substrate. A semiconductor chip and sleeve member are arranged on the substrate and electrically connected to the conductor track. The sleeve member includes a rim with a maximum inner diameter. The module further includes a contact element. The contact element includes a first end arranged within and electrically connected to the sleeve member, a second end providing an external contact of the module, and a section arranged between the first end and the second end. The section includes a maximum outer diameter that is larger than the maximum inner diameter of the rim. The contact element is in mechanical contact with the sleeve member such that the section between both ends of the contact element is arranged outside the sleeve member and borne on the rim of the sleeve member.
Abstract translation: 一个实施例提供具有电绝缘基板的半导体模块。 导体轨道布置在基板上。 半导体芯片和套筒构件布置在基板上并电连接到导体轨道。 套筒构件包括具有最大内径的边缘。 该模块还包括接触元件。 接触元件包括布置在套筒构件内并电连接到套筒构件的第一端，提供模块的外部接触的第二端和布置在第一端和第二端之间的部分。 该部分包括大于轮辋的最大内径的最大外径。 接触元件与套筒构件机械接触，使得接触元件的两端之间的部分布置在套筒构件外部并承载在套筒构件的边缘上。
-
7.发明授权公开(公告)号：US07548825B2
公开(公告)日：2009-06-16
申请号：US11622727
申请日：2007-01-12
Applicant: Reinhold Bayerer , Markus Thoben
Inventor： Reinhold Bayerer , Markus Thoben
CPC classification number: G01R19/0092 , G01K7/30 , H01L23/34 , H01L24/34 , H01L27/0248 , H01L2224/48091 , H01L2224/48472 , H01L2224/49111 , H01L2224/49175 , H01L2924/00014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/15787 , H01L2924/00 , H01L2224/37099
Abstract: A current/temperature measurement method using parasitic components in an electronic power circuit is disclosed. The measured values derived from these parasitic components with inadequate precision are first of all compensated for, in terms of their current/temperature or voltage dependence, during the production process. The evaluation which takes place during operation involves compensating for the temperature or current dependence of the sensor components using two measurements which are linearly independent of one another and appropriate arithmetic operations in an evaluation unit.
Abstract translation: 公开了一种使用电子电路中的寄生元件的电流/温度测量方法。 从这些具有不足精度的寄生分量得到的测量值首先在生产过程中根据其当前/温度或电压依赖性进行补偿。 在操作期间进行的评估包括使用彼此线性相关的两个测量值和评估单元中适当的算术运算来补偿传感器部件的温度或电流依赖性。
-
公开(公告)号：US09661752B2
公开(公告)日：2017-05-23
申请号：US13163200
申请日：2011-06-17
Applicant: Tao Hong , Markus Thoben
Inventor： Tao Hong , Markus Thoben
IPC: H05K7/00 , H05K1/18 , G01R1/20 , H01L23/64 , H01L25/07 , H01L25/16 , H01L25/18 , H01L23/00 , H01L27/02 , H01L49/02 , H05K3/22
CPC classification number: H05K1/181 , G01R1/203 , H01L23/647 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/072 , H01L25/16 , H01L25/18 , H01L27/0207 , H01L28/20 , H01L2224/29339 , H01L2224/32225 , H01L2224/45014 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/8382 , H01L2224/8384 , H01L2224/85205 , H01L2924/00011 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01047 , H01L2924/014 , H01L2924/0781 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H05K3/222 , H05K2201/09663 , H05K2201/0969 , H05K2201/10022 , H05K2201/10166 , H05K2203/173 , Y02P70/611 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/83205
Abstract: A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.
-
公开(公告)号：US20110310568A1
公开(公告)日：2011-12-22
申请号：US13163200
申请日：2011-06-17
Applicant: Tao Hong , Markus Thoben
Inventor： Tao Hong , Markus Thoben
CPC classification number: H05K1/181 , G01R1/203 , H01L23/647 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/072 , H01L25/16 , H01L25/18 , H01L27/0207 , H01L28/20 , H01L2224/29339 , H01L2224/32225 , H01L2224/45014 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/8382 , H01L2224/8384 , H01L2224/85205 , H01L2924/00011 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01047 , H01L2924/014 , H01L2924/0781 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H05K3/222 , H05K2201/09663 , H05K2201/0969 , H05K2201/10022 , H05K2201/10166 , H05K2203/173 , Y02P70/611 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/83205
Abstract: A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.
Abstract translation: 电路装置具有填充电路载体，并且包括在顶侧具有顶侧和图案化金属化层的平坦绝缘载体和布置在金属化层的第一部分上的第一功率半导体芯片。 第一功率半导体芯片具有导电连接到第一部分的第一下部芯片负载端子。 分流电阻器布置在金属化层的第二部分上。 分流电阻器具有导电连接到第二部分的下主端子。 在第一部分和第二部分之间提供导电连接。 导电连接包括第一部分和第二部分之间的收缩部分，使得在电路装置的操作期间在第一下部芯片负载端子和下部主端子之间流动的电流必须通过收缩部。
-
公开(公告)号：US07701051B2
公开(公告)日：2010-04-20
申请号：US11234999
申请日：2005-09-26
Applicant: Reinhold Bayerer , Markus Thoben
Inventor： Reinhold Bayerer , Markus Thoben
IPC: H01L23/12
CPC classification number: H01L23/5385 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/48227 , H01L2224/49111 , H01L2924/00014 , H01L2924/0102 , H01L2924/01068 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A power semiconductor module (1) has power semiconductor components (2, 4, 6, 8, 10, 12) arranged on a substrate (14), at least one portion of which components is connected in parallel and arranged symmetrically on the substrate (14). A second conduction plane (24, 26) is provided for making contact with the power semiconductor components (2, 4, 6, 8, 10, 12). The second conduction plane is arranged in a manner electrically insulated from the substrate surface (16) above the surfaces of the power semiconductor components (2, 4, 6, 8, 10, 12) that are remote from the substrate surface (16).
Abstract translation: 功率半导体模块（1）具有布置在基板（14）上的功率半导体部件（2,4,6,8,10,12），其中至少一部分部件并联连接并对称地布置在基板上 14）。 提供第二导电平面（24,26）以与功率半导体部件（2,4,6,8,10,12）接触。 第二导电平面以远离基板表面（16）的功率半导体部件（2,4,6,8,10,12）的表面之上与基板表面（16）电绝缘的方式布置。
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.011 seconds)
