公开(公告)号：US08102052B2

公开(公告)日：2012-01-24

申请号：US13026326

申请日：2011-02-14

Applicant: Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

Inventor： Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Josef Böck

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract translation: 本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。 在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。 单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。 沉积包括形成两个或更多个子层。 可以为每个单独的子层改变工艺参数以优化沉积特性。

公开(公告)号：US20110133297A1

公开(公告)日：2011-06-09

申请号：US13025552

申请日：2011-02-11

Applicant: Martin FRANOSCH ,  Andreas MECKES ,  Edward FUERGUT

Inventor： Martin FRANOSCH ,  Andreas MECKES ,  Edward FUERGUT

IPC: H01L27/20 ,  H01L29/84 ,  H01L21/60

CPC classification number: B81C1/00269 ,  B81C1/00333 ,  B81C2203/0136 ,  H01L21/50 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/28 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H03H9/0523 ,  H03H9/1007 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor is disclosed. In one embodiment, the semiconductor includes a semiconductor substrate having an active area region, a covering configured to protect the active area region, and a carrier. An interspace is located between the carrier and the covering. The interspace is filled with an underfiller material is disclosed.

Abstract translation: 公开了半导体。 在一个实施例中，半导体包括具有有源区域区域的半导体衬底，被配置为保护有源区域区域的覆盖物和载体。 一个间隙位于载体和覆盖物之间。 公开了填充有底填料的间隙。

公开(公告)号：US20060191868A1

公开(公告)日：2006-08-31

申请号：US11346605

申请日：2006-02-02

Applicant: Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

Inventor： Martin Franosch ,  Andreas Meckes ,  Klaus-Guenter Oppermann

IPC: B44C1/22 ,  H01L21/302 ,  C23F1/00

CPC classification number: B81C1/00539 ,  B81B2203/0127

Abstract: In the inventive method for the wet-chemical removal of a sacrificial material in a material structure, there is first provided the material structure, wherein the material structure has a treatment region with the sacrificial material accessible through an opening. Subsequently, the sacrificial material is brought into contact with a wet-chemical treatment agent through the opening for the removal of the sacrificial material, wherein a mechanical vibration is generated in the wet-chemical treatment agent or in the wet-chemical treatment agent and the material structure during the contacting of the sacrificial material with the wet-chemical treatment agent.

Abstract translation: 在用于在材料结构中湿化学去除牺牲材料的本发明的方法中，首先提供材料结构，其中材料结构具有处理区域，其中牺牲材料可通过开口接近。 随后，牺牲材料通过用于去除牺牲材料的开口与湿化学处理剂接触，其中在湿化学处理剂或湿化学处理剂中产生机械振动， 在牺牲材料与湿化学处理剂接触期间的材料结构。

公开(公告)号：US20050148205A1

公开(公告)日：2005-07-07

申请号：US10821798

申请日：2004-04-09

Applicant: Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann

Inventor： Martin Franosch ,  Andreas Meckes ,  Klaus-Gunter Oppermann

IPC: H03H3/02 ,  H03H3/08 ,  H03H9/10 ,  H01L21/00

CPC classification number: B81C1/00333 ,  B81C2203/0136 ,  H03H3/02 ,  H03H3/08 ,  H03H9/105 ,  H03H9/1092 ,  Y10S156/93 ,  Y10S438/976 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224 ,  Y10T29/49798 ,  Y10T156/1082 ,  Y10T156/11

Abstract: In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the sacrificial structure comprises a first portion covering a first area of the substrate including the device and a second portion extending from the first portion into a second area of the substrate including no device. Then a first cover layer is deposited that encloses the sacrificial structure such that the second portion of the sacrificial structure is at least partially exposed. Then the sacrificial structure is removed, and the structure formed by the removal of the sacrificial structure is closed.

Abstract translation: 在用于生产用于形成在衬底中的器件的保护罩的方法中，首先在衬底上产生牺牲结构，其中牺牲结构包括覆盖包括该器件的衬底的第一区域的第一部分和延伸 从第一部分到不包括器件的衬底的第二区域。 然后沉积包围牺牲结构的第一覆盖层，使得牺牲结构的第二部分至少部分地暴露。 然后去除牺牲结构，并且通过去除牺牲结构形成的结构是封闭的。

公开(公告)号：US06548846B2

公开(公告)日：2003-04-15

申请号：US09734466

申请日：2000-12-11

Applicant: Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

Inventor： Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

IPC: H01L27108

CPC classification number: H01L27/1085 ,  H01L27/10805

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Abstract translation: 用于DRAM的存储电容器具有由氮化硅构成的电介质，并且在电介质上具有彼此相对设置的至少两个电极。 对于电极，使用在材料的费米能级和电介质的导带之间具有高隧道势垒的材料。 用于电极的合适材料是金属如铂，钨和铱或硅化物。

公开(公告)号：US6159815A

公开(公告)日：2000-12-12

申请号：US269311

申请日：1999-06-04

Applicant: Bernhard Lustig ,  Herbert Schafer ,  Martin Franosch

Inventor： Bernhard Lustig ,  Herbert Schafer ,  Martin Franosch

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66636 ,  H01L21/823864

Abstract: In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.

Abstract translation: PCT No.PCT / DE97 / 01933 Sec。 371日期1999年6月4日第 102（e）1999年6月4日PCT PCT 1996年9月3日PCT公布。 公开号WO98 / 13865 日期1998年4月2日为了生产具有HDD配置文件和LDD配置文件的MOS晶体管，首先在LDD配置文件的区域中形成HDD配置文件，然后是LDD配置文件，以生成陡峭的掺杂剂配置文件。 LDD分布优选通过蚀刻和原位掺杂的选择性外延生长。

公开(公告)号：US6040995A

公开(公告)日：2000-03-21

申请号：US230614

申请日：1999-01-28

Applicant: Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

Inventor： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

IPC: H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02

CPC classification number: H01L29/513 ,  H01L29/518 ,  H01L29/792

Abstract: For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

Abstract translation: PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层​​分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

公开(公告)号：US6022786A

公开(公告)日：2000-02-08

申请号：US32484

申请日：1998-02-27

Applicant: Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

Inventor： Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

IPC: H01L21/306 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10861

Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Abstract translation: 为了制造电容器，特别是用于动态存储单元布置，在衬底中蚀刻沟槽。 在沟槽中，产生层序列，其交替地包含掺杂的硅和含锗层的层。 通过各向异性蚀刻，半导体衬底（12）的表面暴露在沟槽底板的区域中。 沟槽填充有导电支撑结构（20）。 含锗层被选择性地去除掺杂硅层。 掺杂硅（17）和支撑结构（20）的层的暴露表面设置有电容器电介质（22），其上施加有对电极（23）。

公开(公告)号：US08329532B2

公开(公告)日：2012-12-11

申请号：US13314595

申请日：2011-12-08

Applicant: Herbert Schaefer ,  Martin Franosch ,  Thomas Meister ,  Josef Boeck

Inventor： Herbert Schaefer ,  Martin Franosch ,  Thomas Meister ,  Josef Boeck

IPC: H01L21/8238

CPC classification number: H01L21/02639 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02661

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

公开(公告)号：US08148055B2

公开(公告)日：2012-04-03

申请号：US11771898

申请日：2007-06-29

Applicant: Klaus-Guenter Oppermann ,  Martin Franosch

Inventor： Klaus-Guenter Oppermann ,  Martin Franosch

IPC: G03F7/32 ,  G03F7/42

CPC classification number: G03F7/325 ,  G03F7/322 ,  G03F7/40

Abstract: A method for developing a photoresist includes applying a first developer to the photoresist to remove non-cross-linked areas of the photoresist, and applying a second developer to the photoresist to remove remaining non-cross-linked areas of the photoresist, wherein the first developer and the second developer differ in their compositions.

Abstract translation: 用于显影光致抗蚀剂的方法包括将第一显影剂施加到光致抗蚀剂以去除光致抗蚀剂的非交联区域，以及将第二显影剂施加到光致抗蚀剂以除去光致抗蚀剂的剩余非交联区域，其中第一 开发者和第二个开发者的组成不同。