Multi-wave band light sensor combined with function of IR sensing and method of fabricating the same
    2.
    发明授权
    Multi-wave band light sensor combined with function of IR sensing and method of fabricating the same 有权
    多波段光传感器结合IR感测功能及其制作方法

    公开(公告)号:US09136301B2

    公开(公告)日:2015-09-15

    申请号:US14020908

    申请日:2013-09-09

    Abstract: Provided is a multi-wave band light sensor combined with a function of infrared ray (IR) sensing including a substrate, an IR sensing structure, a dielectric layer, and a multi-wave band light sensing structure. The substrate includes a first region and a second region. The IR sensing structure is in the substrate for sensing IR. The dielectric layer is on the IR sensing structure. The multi-wave band light sensing structure includes a first wave band light sensor, a second wave band light sensor, and a third wave band light sensor. The second wave band light sensor and the first wave band light sensor are overlapped and disposed on the IR sensing structure on the first region of the substrate from the bottom up. The third wave band light sensor is in the dielectric layer of the second region.

    Abstract translation: 提供了与包括基板,IR感测结构,电介质层和多波段光感测结构的红外线(IR)感测功能相结合的多波段光束传感器。 衬底包括第一区域和第二区域。 IR感测结构位于用于感测IR的基板中。 电介质层位于IR感测结构上。 多波段光束感测结构包括第一波段光传感器,第二波段光传感器和第三波段光传感器。 第二波段光传感器和第一波段光传感器从底部向上叠置并设置在基板的第一区域上的IR感测结构上。 第三波段光传感器位于第二区域的介质层中。

    TRENCH LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    3.
    发明申请
    TRENCH LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
    TRENCH横向扩散金属氧化物半导体器件及其制造方法

    公开(公告)号:US20160211348A1

    公开(公告)日:2016-07-21

    申请号:US14601242

    申请日:2015-01-21

    Inventor: Kosuke Yoshida

    Abstract: A trench lateral diffusion metal oxide semiconductor (LDMOS) device, disposed on a substrate, comprising: a transistor and an LDMOS transistor. The transistor has a gate. The LDMOS transistor has a trench gate, wherein the trench gate protrudes from a surface of the substrate. Electrical connection of the trench gate and a doping region due to a metal silicide may be prevented by protruding the trench gate from the surface of the substrate. And furthermore a step height difference between a gate and the trench gate may be decreased, and openings respectively exposing a top portion of the trench gate and a top portion of the gate may be formed without changing the manufacturing conditions.

    Abstract translation: 设置在基板上的沟槽横向扩散金属氧化物半导体(LDMOS)器件,包括:晶体管和LDMOS晶体管。 晶体管有一个门。 LDMOS晶体管具有沟槽栅极,其中沟槽栅极从衬底的表面突出。 通过从衬底的表面突出沟槽栅极可以防止由于金属硅化物引起的沟槽栅极和掺杂区域的电连接。 此外,可以减小栅极和沟槽栅极之间的台阶高度差,并且可以在不改变制造条件的情况下形成分别暴露沟槽栅极的顶部和栅极顶部的开口。

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    4.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号:US20150024562A1

    公开(公告)日:2015-01-22

    申请号:US14505510

    申请日:2014-10-03

    CPC classification number: H01L29/66825 H01L27/11517 H01L27/11526 H01L28/20

    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

    Abstract translation: 提供一种形成半导体结构的方法。 提供具有单元区域和周边区域的基板。 在单元区域中的基板上形成包括栅极氧化物层,浮置栅极和第一间隔物的层叠结构,并且在周边区域的基板上形成电阻体。 在堆叠结构旁边的衬底中形成至少两个掺杂区域。 介电材料层和导电材料层依次形成在基板上。 在衬底上形成图案化的光致抗蚀剂层以覆盖堆叠结构和电阻器的一部分。 除去图案化的光致抗蚀剂层未被覆盖的电介质材料层和导电材料层,以在叠层结构上形成栅极间电介质层和控制栅极,同时在电阻器上形成自对准硅化物阻挡层。

    Light sensor
    5.
    发明授权
    Light sensor 有权
    光传感器

    公开(公告)号:US09142583B2

    公开(公告)日:2015-09-22

    申请号:US14089769

    申请日:2013-11-26

    Abstract: Provided is a light sensor including a substrate, a dielectric layer, a plurality of pixels, a plurality of spacers, and a plurality of metal interconnects. The dielectric layer is located on the substrate. The pixels are located in the dielectric layer. The spacers are located on the sidewall of openings between adjacent pixels. The metal interconnects are located in the openings and cover the spacers so as to be electrically connected to the corresponding pixels.

    Abstract translation: 提供一种光传感器,其包括基板,电介质层,多个像素,多个间隔物和多个金属互连。 电介质层位于衬底上。 像素位于电介质层中。 间隔物位于相邻像素之间的开口的侧壁上。 金属互连件位于开口中并且覆盖间隔件以便电连接到相应的像素。

    LIGHT SENSOR
    6.
    发明申请
    LIGHT SENSOR 有权
    光传感器

    公开(公告)号:US20150091123A1

    公开(公告)日:2015-04-02

    申请号:US14089769

    申请日:2013-11-26

    Abstract: Provided is a light sensor including a substrate, a dielectric layer, a plurality of pixels, a plurality of spacers, and a plurality of metal interconnects. The dielectric layer is located on the substrate. The pixels are located in the dielectric layer. The spacers are located on the sidewall of openings between adjacent pixels. The metal interconnects are located in the openings and cover the spacers so as to be electrically connected to the corresponding pixels.

    Abstract translation: 提供一种光传感器,其包括基板,电介质层,多个像素,多个间隔物和多个金属互连。 电介质层位于衬底上。 像素位于电介质层中。 间隔物位于相邻像素之间的开口的侧壁上。 金属互连件位于开口中并且覆盖间隔件以便电连接到相应的像素。

    High voltage bootstrap gate driving apparatus
    7.
    发明授权
    High voltage bootstrap gate driving apparatus 有权
    高压自举门驱动装置

    公开(公告)号:US09379696B2

    公开(公告)日:2016-06-28

    申请号:US14294176

    申请日:2014-06-03

    Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.

    Abstract translation: 提供了一种高压自举门驱动装置。 栅极驱动装置包括高端晶体管,低端晶体管,缓冲器,升压电容器和高电压耗尽晶体管。 高端晶体管接收第一电源电压。 缓冲器根据偏置电压向高端晶体管提供高端驱动信号。 升压电容器串联耦合在基极电压和偏置电压之间。 耗尽晶体管的第一端耦合到第二电源电压,耗尽型晶体管的第二端耦合到偏置电压,耗尽晶体管的控制端接收参考接地电压。

    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开
    半导体结构及其形成方法

    公开(公告)号:US20150333140A1

    公开(公告)日:2015-11-19

    申请号:US14277809

    申请日:2014-05-15

    Inventor: Kosuke Yoshida

    Abstract: A semiconductor structure is provided. An N-type epitaxial layer is disposed on an N-type substrate. The N-type epitaxial layer has at least one trench therein, wherein the trench has a straight sidewall. A first insulating layer is disposed on at least a portion of a surface of the trench. A silicon-containing layer is disposed in a lower portion of the trench and has at least one air gap therein. A first conductive layer is disposed in an upper portion of the trench. Two P-type well regions are disposed in the N-type epitaxial layer beside the trench. Two N-type source regions are respectively disposed in the P-type well regions beside the trench.

    Abstract translation: 提供半导体结构。 在N型衬底上设置N型外延层。 N型外延层在其中具有至少一个沟槽,其中沟槽具有直的侧壁。 第一绝缘层设置在沟槽的表面的至少一部分上。 含硅层设置在沟槽的下部,并在其中具有至少一个气隙。 第一导电层设置在沟槽的上部。 在沟槽旁边的N型外延层中设置两个P型阱区。 两个N型源极区域分别设置在沟槽旁边的P型阱区域中。

    MULTI-WAVE BAND LIGHT SENSOR COMBINED WITH FUNCTION OF IR SENSING AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    MULTI-WAVE BAND LIGHT SENSOR COMBINED WITH FUNCTION OF IR SENSING AND METHOD OF FABRICATING THE SAME 有权
    与红外感应功能相结合的多波段光传感器及其制作方法

    公开(公告)号:US20140008653A1

    公开(公告)日:2014-01-09

    申请号:US14020908

    申请日:2013-09-09

    Abstract: Provided is a multi-wave band light sensor combined with a function of infrared ray (IR) sensing including a substrate, an IR sensing structure, a dielectric layer, and a multi-wave band light sensing structure. The substrate includes a first region and a second region. The IR sensing structure is in the substrate for sensing IR. The dielectric layer is on the IR sensing structure. The multi-wave band light sensing structure includes a first wave band light sensor, a second wave band light sensor, and a third wave band light sensor. The second wave band light sensor and the first wave band light sensor are overlapped and disposed on the IR sensing structure on the first region of the substrate from the bottom up. The third wave band light sensor is in the dielectric layer of the second region.

    Abstract translation: 提供了与包括基板,IR感测结构,电介质层和多波段光感测结构的红外线(IR)感测功能相结合的多波段光束传感器。 衬底包括第一区域和第二区域。 IR感测结构位于用于感测IR的基板中。 电介质层位于IR感测结构上。 多波段光束感测结构包括第一波段光传感器,第二波段光传感器和第三波段光传感器。 第二波段光传感器和第一波段光传感器从底部向上叠置并设置在基板的第一区域上的IR感测结构上。 第三波段光传感器位于第二区域的介质层中。

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