公开(公告)号：US08832343B2

公开(公告)日：2014-09-09

申请号：US13550715

申请日：2012-07-17

Applicant: Michael Decesaris ,  Jeffrey M. Franke ,  Luke D. Remis ,  John K. Whetzel

Inventor： Michael Decesaris ,  Jeffrey M. Franke ,  Luke D. Remis ,  John K. Whetzel

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F2213/0016

Abstract: An I2C system comprises an inter-integrated circuit (I2C) master device coupled to an I2C multiplexer via a master I2C bus. A plurality of slave I2C busses emanating from the I2C multiplexer couple the I2C multiplexer to a plurality of I2C slave devices. Each of the slave I2C busses comprises a serial data (SDA) line and serial clock (SCL) line. Each of the slave I2C busses, which is coupled to two I2C slave devices, has a first channel and a second channel. The first channel puts bidirectional serial data on the SDA line and clock signals on the SCL line, and the second channel puts bidirectional serial data on the SCL line and clock signals on the SDA line. A channel selector, associated with the I2C multiplexer, selectively couples the I2C master device to one of the two I2C slave devices via the first channel or the second channel.

Abstract translation: I2C系统包括通过主I2C总线耦合到I2C多路复用器的集成电路（I2C）主器件。 从I2C多路复用器发出的多个从属I2C总线将I2C多路复用器耦合到多个I2C从器件。 每个从I2C总线包括串行数据（SDA）线和串行时钟（SCL）线。 耦合到两个I2C从器件的每个从I2C总线具有第一通道和第二通道。 第一个通道将SDA线上的双向串行数据和SCL线上的时钟信号放在一起，第二个通道将SCL线上的双向串行数据和SDA线上的时钟信号。 与I2C多路复用器相关的通道选择器通过第一通道或第二通道将I2C主器件选择性地耦合到两个I2C从器件中的一个。

公开(公告)号：US20140013151A1

公开(公告)日：2014-01-09

申请号：US13541750

申请日：2012-07-04

Applicant: Michael DeCesaris ,  Luke D. Remis ,  Gregory D. Sellman ,  Steven L. Vanderlinden

Inventor： Michael DeCesaris ,  Luke D. Remis ,  Gregory D. Sellman ,  Steven L. Vanderlinden

IPC: G06F1/04 ,  G06F13/36

CPC classification number: G06F13/4282

Abstract: In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.

Abstract translation: 根据本发明的一个实施例，可以提供用于I2C总线接口的I2C总线复用电路。 I2C总线复用电路可以通过I2C总线从I2C主器件检测启动命令，缓冲来自I2C主器件的数据，检测总线串行时钟（SCL）线的时钟频率，从而有助于I2C总线接口中的多路开关切换 的I2C主器件，将I2C主器件的串行数据（SDA）线保持在时钟拉伸状态，并根据检测到的I2C主器件SCL的时钟频率选择一个端口。 该方法还可以包括将所缓冲的数据发送到所选端口上的I2C从设备。 该方法还可以包括从所选端口上的I2C从设备接收确认。

公开(公告)号：US20130304954A1

公开(公告)日：2013-11-14

申请号：US13467332

申请日：2012-05-09

Applicant: MICHAEL DECESARIS ,  STEVEN C. JACOBSON ,  LUKE D. REMIS ,  GREGORY D. SELLMAN

Inventor： MICHAEL DECESARIS ,  STEVEN C. JACOBSON ,  LUKE D. REMIS ,  GREGORY D. SELLMAN

IPC: G06F13/00

CPC classification number: G06F1/324 ,  G06F9/44 ,  G06F13/38 ,  G06F13/4282

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract translation: 优化I2C总线频率，总线包括耦合主节点和从节点的信号线，耦合到上升时间检测电路的信号线监视信号线的电压，电压在逻辑低电平和逻辑高电平之间交替，其中优化 频率包括：在信号线上升期间检测第一电压，第一电压大于逻辑低电压; 启动一个计数器，为电路的每个时钟周期增加一次; 检测信号线上的第二电压，第二电压大于第一电压并小于逻辑高电平; 停止柜台 根据时钟周期和计数器值计算上升时间; 确定上升时间是否大于最大阈值; 并且如果计算的上升时间大于最大阈值，则增加I2C总线频率。

公开(公告)号：US09015394B2

公开(公告)日：2015-04-21

申请号：US13530284

申请日：2012-06-22

Applicant: Michael DeCesaris ,  Steven C. Jacobson ,  Luke D. Remis ,  Gregory D. Sellman

Inventor： Michael DeCesaris ,  Steven C. Jacobson ,  Luke D. Remis ,  Gregory D. Sellman

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/40 ,  H03M1/34

CPC classification number: G06F13/4291 ,  G06F1/3215 ,  G06F11/349 ,  G06F13/4282 ,  H03M1/34

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract translation: 包括SPI主机，CS乘法器，多个SPI从机以及下降时间检测电路的SPI系统中的片选（'CS'）相乘，其中SPI主机耦合到CS乘法器和下降时间检测 CS乘法器包括多个CS输出，每个CS输出耦合到SPI从机，CS乘法包括：从SPI主机接收CS信号线上的CS信号; 检测CS信号的下降时间; 并且如果CS信号的下降时间小于预定阈值，则由下降时间检测电路配置CS乘法器，以便在第一CS输出上提供CS信号以在第二CS输出上提供CS信号 CS输出。

公开(公告)号：US08767370B2

公开(公告)日：2014-07-01

申请号：US13557418

申请日：2012-07-25

Applicant: Michael DeCesaris ,  John A. Henise, IV ,  Luke D. Remis ,  Gregory D. Sellman

Inventor： Michael DeCesaris ,  John A. Henise, IV ,  Luke D. Remis ,  Gregory D. Sellman

IPC: H02H1/04 ,  H02H9/00

CPC classification number: H02H9/005 ,  H02H1/04 ,  H02H3/08 ,  H04L25/03878

Abstract: Providing noise protection in a signal transmission system that includes a first component, second component, controller, switch, and pre-charged capacitor, the first and second components coupled by a signal line, the controller coupled to the switch, the switch configured to couple the signal line to the capacitor when activated, where providing noise protection includes: determining, by the controller, that a signal transmitted on the signal line transitioned to a steady state voltage; enabling, by the controller responsive to determining that the signal transitioned to the steady state voltage, noise protection to the signal on the signal line including activating the switch thereby coupling the signal line to the pre-charged capacitor, the pre-charged capacitor providing noise protection to the signal on the signal line; and prior to the signal on the signal line transitioning from the steady state voltage, deactivating the switch, thereby decoupling the signal line from the pre-charged capacitor.

Abstract translation: 在包括第一组件，第二组件，控制器，开关和预充电电容器的信号传输系统中提供噪声保护，所述第一和第二组件通过信号线耦合，所述控制器耦合到所述开关，所述开关被配置为耦合 当激活时到电容器的信号线，其中提供噪声保护包括：由控制器确定在信号线上传输的信号转变为稳态电压; 所述控制器响应于确定所述信号转换到所述稳态电压，对所述信号线上的信号进行噪声保护，包括启动所述开关，从而将所述信号线耦合到所述预充电电容器，所述预充电电容器提供噪声 保护信号线上的信号; 并且在信号线上的信号从稳态电压转变之前，停用开关，从而使信号线与预充电电容器分离。

公开(公告)号：US20140029693A1

公开(公告)日：2014-01-30

申请号：US13557418

申请日：2012-07-25

Applicant: Michael DeCesaris ,  John A. Henise, IV ,  Luke D. Remis ,  Gregory D. Sellman

Inventor： Michael DeCesaris ,  John A. Henise, IV ,  Luke D. Remis ,  Gregory D. Sellman

IPC: H04L25/03

CPC classification number: H02H9/005 ,  H02H1/04 ,  H02H3/08 ,  H04L25/03878

Abstract: Providing noise protection in a signal transmission system that includes a first component, second component, controller, switch, and pre-charged capacitor, the first and second components coupled by a signal line, the controller coupled to the switch, the switch configured to couple the signal line to the capacitor when activated, where providing noise protection includes: determining, by the controller, that a signal transmitted on the signal line transitioned to a steady state voltage; enabling, by the controller responsive to determining that the signal transitioned to the steady state voltage, noise protection to the signal on the signal line including activating the switch thereby coupling the signal line to the pre-charged capacitor, the pre-charged capacitor providing noise protection to the signal on the signal line; and prior to the signal on the signal line transitioning from the steady state voltage, deactivating the switch, thereby decoupling the signal line from the pre-charged capacitor.

Abstract translation: 在包括第一组件，第二组件，控制器，开关和预充电电容器的信号传输系统中提供噪声保护，所述第一和第二组件通过信号线耦合，所述控制器耦合到所述开关，所述开关被配置为耦合 当激活时到电容器的信号线，其中提供噪声保护包括：由控制器确定在信号线上传输的信号转变为稳态电压; 所述控制器响应于确定所述信号转换到所述稳态电压，对所述信号线上的信号进行噪声保护，包括启动所述开关，从而将所述信号线耦合到所述预充电电容器，所述预充电电容器提供噪声 保护信号线上的信号; 并且在信号线上的信号从稳态电压转变之前，停用开关，从而使信号线与预充电电容器分离。

公开(公告)号：US20140013017A1

公开(公告)日：2014-01-09

申请号：US13541749

申请日：2012-07-04

Applicant: Michael DeCesaris ,  Pravin S. Patel ,  Luke D. Remis ,  Gregory D. Sellman

Inventor： Michael DeCesaris ,  Pravin S. Patel ,  Luke D. Remis ,  Gregory D. Sellman

IPC: G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4027 ,  G06F13/4282

Abstract: A method, device and computer program product for providing multi-protocol communication on an inter-integrated circuit (I2C) bus. The method for providing multi-protocol communication on an inter-integrated circuit (I2C) bus can include issuing a start command by a bus management device onto the I2C bus. Thereafter, the bus management device can send an embedded differential protocol to a non-I2C device. Once communication with the non-I2C device is completed, the bus management device can issue a stop command to release the I2C bus. In one aspect of this embodiment, the method can include receiving a response from the non-I2C device.

Abstract translation: 一种用于在集成电路（I2C）总线上提供多协议通信的方法，设备和计算机程序产品。 在集成电路（I2C）总线上提供多协议通信的方法可以包括由总线管理装置向I2C总线发出启动命令。 此后，总线管理装置可以向非I2C设备发送嵌入式差分协议。 一旦与非I2C设备的通信完成，总线管理设备就可以发出停止命令来释放I2C总线。 在该实施例的一个方面，该方法可以包括从非I2C设备接收响应。

公开(公告)号：US20130346658A1

公开(公告)日：2013-12-26

申请号：US13530284

申请日：2012-06-22

Applicant: Michael DeCesaris ,  Steven C. Jacobson ,  Luke D. Remis ,  Gregory D. Sellman

Inventor： Michael DeCesaris ,  Steven C. Jacobson ,  Luke D. Remis ,  Gregory D. Sellman

IPC: G06F13/40

CPC classification number: G06F13/4291 ,  G06F1/3215 ,  G06F11/349 ,  G06F13/4282 ,  H03M1/34

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract translation: 包括SPI主机，CS乘法器，多个SPI从机以及下降时间检测电路的SPI系统中的片选（'CS'）相乘，其中SPI主机耦合到CS乘法器和下降时间检测 CS乘法器包括多个CS输出，每个CS输出耦合到SPI从机，CS乘法包括：从SPI主机接收CS信号线上的CS信号; 检测CS信号的下降时间; 并且如果CS信号的下降时间小于预定阈值，则由下降时间检测电路配置CS乘法器，以便在第一CS输出上提供CS信号以在第二CS输出上提供CS信号 CS输出。

公开(公告)号：US20130272515A1

公开(公告)日：2013-10-17

申请号：US13444389

申请日：2012-04-11

Applicant: Michael DeCesaris ,  William M. Megarity ,  Luke D. Remis ,  Gregory D. Sellman

Inventor： Michael DeCesaris ,  William M. Megarity ,  Luke D. Remis ,  Gregory D. Sellman

IPC: H04M3/42

CPC classification number: H04W4/16 ,  H04M3/436

Abstract: Selectively filtering incoming communications events in a communications device, including: receiving, by a communications event filtering module, an incoming communications event; determining, by the communications event filtering module, whether the communications device is currently servicing a call; responsive to determining that the communications device is currently servicing a call, determining, by the communications event filtering module, whether the call is interruptible; and responsive to determining that the call is not interruptible, blocking, by the communications event filtering module, the incoming communications event from presentation by the communications device until the call has ended.

Abstract translation: 在通信设备中选择性地过滤进入的通信事件，包括：由通信事件过滤模块接收进入的通信事件; 由所述通信事件过滤模块确定所述通信设备当前是否正在服务于呼叫; 响应于确定所述通信设备当前正在服务于呼叫，由所述通信事件过滤模块确定所述呼叫是否可中断; 并且响应于确定所述呼叫不可中断，所述通信事件过滤模块阻止所述通信设备的呼入通信事件，直到所述呼叫结束为止。

公开(公告)号：US09098645B2

公开(公告)日：2015-08-04

申请号：US13530473

申请日：2012-06-22

Applicant: Michael Decesaris ,  Luke D. Remis ,  Gregory D. Sellman

Inventor： Michael Decesaris ,  Luke D. Remis ,  Gregory D. Sellman

IPC: G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F13/42

CPC classification number: G06F13/4291 ,  G06F2213/0016

Abstract: Increasing data transmission rate in an I2C system that includes an I2C source device and an destination device, the source device coupled to the destination device through an SDL and SCL, including: receiving in parallel, by the destination device, an SDL data signal and an SCL data signal, the SCL data signal encoded with bits; and, for each bit of the SCL data signal: detecting rise time of the bit and determining, in dependence upon the detected rise time, whether the bit represents a first binary value or a second binary value including: determining that the bit represents a first binary value when the detected rise time is less than a predefined threshold; and determining that the bit represents a second binary value when the detected rise time is not less than the predefined threshold.

Abstract translation: 包括I2C源设备和目标设备的I2C系统中的数据传输速率提高，源设备通过SDL和SCL耦合到目标设备，包括：由目标设备并行接收SDL数据信号和 SCL数据信号，SCL数据信号用位编码; 并且对于SCL数据信号的每一位：检测位的上升时间，并且根据检测到的上升时间确定该位是否表示第一二进制值或第二二进制值，包括：确定该位表示第一个 当检测到的上升时间小于预定阈值时，二进制值; 以及当所检测的上升时间不小于所述预定阈值时，确定所述比特表示第二二进制值。