公开(公告)号：US10672453B2

公开(公告)日：2020-06-02

申请号：US15911586

申请日：2018-03-05

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Ting-Shuo Hsu

IPC: G11C5/14 ,  G11C11/4074 ,  G11C29/56

Abstract: The present disclosure provides a charge pump system and a method of operating the same. The charge pump system includes a first pump circuit, a second pump circuit and a control device. The first pump circuit is configured to operate in a first voltage domain. The second pump circuit is configured to operate in a second voltage domain different from the first voltage domain. The control device is configured to selectively enable one of the first pump circuit and the second pump circuit based on an operating environment, wherein the one of the first pump circuit and the second pump circuit provides a pump voltage.

公开(公告)号：US20190272864A1

公开(公告)日：2019-09-05

申请号：US15911586

申请日：2018-03-05

Applicant: NANYA TECHNOLOGY CORP.

Inventor： TING-SHUO HSU

IPC: G11C11/4074 ,  G11C5/14 ,  G11C29/56

Abstract: The present disclosure provides a charge pump system and a method of operating the same. The charge pump system includes a first pump circuit, a second pump circuit and a control device. The first pump circuit is configured to operate in a first voltage domain. The second pump circuit is configured to operate in a second voltage domain different from the first voltage domain. The control device is configured to selectively enable one of the first pump circuit and the second pump circuit based on an operating environment, wherein the one of the first pump circuit and the second pump circuit provides a pump voltage.

公开(公告)号：US09779957B2

公开(公告)日：2017-10-03

申请号：US14447634

申请日：2014-07-31

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/76224

Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

公开(公告)号：US09691773B2

公开(公告)日：2017-06-27

申请号：US14069396

申请日：2013-11-01

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shyam Surthi ,  Lars Heineck

IPC: H01L29/78 ,  H01L27/108 ,  H01L23/522

CPC classification number: H01L27/10891 ,  H01L23/5222 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.

公开(公告)号：US20170018305A1

公开(公告)日：2017-01-19

申请号：US14798471

申请日：2015-07-14

Applicant: Nanya Technology Corp.

Inventor： Da-Zen Chuang ,  Chi-Hsiang Kuo

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0035

Abstract: An electronic apparatus comprising a unified non-volatile memory and a control unit is disclosed. The unified non-volatile memory comprises a first memory section, served as a read only memory; and a second memory section, served as a random access memory. The control unit controls the unified non-volatile memory. The first memory section further comprises: a first area for the first memory section; and a second area for the first memory section. The control unit adjusts a refresh rate of the second memory section according to an amount of access times of the second memory section.

Abstract translation: 公开了一种包括统一的非易失性存储器和控制单元的电子设备。 统一的非易失性存储器包括作为只读存储器的第一存储器部分; 以及作为随机存取存储器的第二存储器部分。 控制单元控制统一的非易失性存储器。 第一存储器部分还包括：用于第一存储器部分的第一区域; 以及用于第一存储器部分的第二区域。 控制单元根据第二存储器部分的访问次数来调整第二存储器部分的刷新率。

公开(公告)号：US20160093532A1

公开(公告)日：2016-03-31

申请号：US14963252

申请日：2015-12-09

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Po-Chun Lin

IPC: H01L21/768 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L23/481 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

Abstract translation: 一种通过堆叠结构制造硅的方法。 提供多个基板。 在每个基板的一个表面上形成至少一个锥形孔。 每个锥形孔填充有锥形的硅通孔。 在每个锥形硅通孔的较宽端部上形成有凹部。 去除衬底的一部分，直到每个锥形硅通孔的较窄端从衬底的另一表面突出。 通过将一个基板上的每个锥形通孔的较窄端部通过另一个基板接合并连接到锥形通过硅通孔的相应凹部中，将基板彼此堆叠。

公开(公告)号：US09093471B2

公开(公告)日：2015-07-28

申请号：US14534192

申请日：2014-11-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

Abstract: A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate.

Abstract translation: 一种形成沟槽MOS结构的方法。 首先，提供衬底，外延层，掺杂区和掺杂阱。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 栅极沟槽穿透掺杂区域和掺杂阱。 部分去除掺杂阱以形成栅极沟槽的底部。 形成栅极隔离以覆盖底部的内壁和栅极沟槽的顶部。 栅极沟槽填充有导电材料以形成沟槽栅极。

公开(公告)号：US09069253B2

公开(公告)日：2015-06-30

申请号：US13801945

申请日：2013-03-13

Applicant: Nanya Technology Corp.

Inventor： Yu-Mei Ni ,  Chun-Yen Huang ,  Pei-Cheng Fan

IPC: G03F1/22 ,  G03F1/24

CPC classification number: G03F1/22 ,  G03F1/24

Abstract: A mask structure, including a substrate; an absorber layer formed on the substrate; and a patterned reflection layer formed on the absorber layer. Optionally, the mask structure may further include a buffer layer, a conductive coating, or combinations thereof. The buffer layer may be formed between the absorber layer and the reflection layer, and the conductive coating may be formed at a back side of the substrate.

Abstract translation: 一种掩模结构，包括基底; 形成在所述基板上的吸收体层; 以及形成在吸收体层上的图案化反射层。 任选地，掩模结构还可以包括缓冲层，导电涂层或其组合。 缓冲层可以形成在吸收层和反射层之间，并且导电涂层可以形成在衬底的背面。

公开(公告)号：US20150155367A1

公开(公告)日：2015-06-04

申请号：US14616750

申请日：2015-02-09

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Wei-Ming Liao

IPC: H01L29/66 ,  H01L21/265 ,  H01L27/108 ,  H01L21/28

CPC classification number: H01L29/66666 ,  H01L21/265 ,  H01L21/28008 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/76

Abstract: A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.

Abstract translation: 沟槽从半导体衬底的主表面延伸到预定深度。 在沟槽中形成栅极氧化层。 掩埋栅电极形成在沟槽的下部。 掩埋栅极电极被覆盖有介电层。 衬底层和硬掩模层形成在半导体衬底上。 通过焊盘层和硬掩模层并进入半导体衬底的凹陷形成在沟槽的一侧。 介电层的一部分露出在凹槽内。 然后去除硬掩模层。 执行离子注入工艺以在沟槽的两侧上注入掺杂剂，由此形成源极掺杂区域和漏极掺杂区域。 源极掺杂区域具有比漏极掺杂区域深的结深度。

公开(公告)号：US20150044852A1

公开(公告)日：2015-02-12

申请号：US14525228

申请日：2014-10-28

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chun-I Hsieh ,  Chang-Rong Wu ,  Neng-Tai Shih

IPC: H01L45/00

CPC classification number: H01L45/165 ,  H01L45/08 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1641

Abstract: An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.

Abstract translation: RRAM包括在形成介电层之后，在电介质层上的处理中包括电介质层和剩余的氧离子或氮离子的电阻层。 当RRAM被施加电压时，氧离子或氮离子占据电介质层中的空位以增加电阻层的电阻。 当RRAM施加另一电压时，从空位中去除氧离子或氮离子以降低电阻层的电阻。